 Yuzhen ZhouandByron Hsu
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4a279d9c36
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[R3] Avoid implicit CUDA sync in routed experts DP slicing (#24550)
Co-authored-by: Byron Hsu <byronhsu1230@gmail.com>
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2026-05-06 18:37:36 -07:00 |
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Yuzhen Zhou
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6b876a7710
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[ROCM][RL] Shuffle Weight In-Place to Preserve Parameter Attributes (#21825)
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2026-04-02 23:43:55 -07:00 |
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Yuzhen Zhou
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b719219de9
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[ROCm] Use unreg path for aiter custom all-reduce during CUDA graph capture (#20155)
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2026-03-09 01:09:04 -07:00 |
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Yuzhen Zhou
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63003a39cf
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[BUG] Support tuple hidden_states from fused MXFP4/FP8 quantization (#19643)
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2026-03-02 20:39:06 -08:00 |
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Yuzhen Zhou
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4f3dc1ef5b
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[ROCm] Use unreg path for custom all-reduce during CUDA graph capture (#19162)
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2026-02-22 23:27:31 -08:00 |
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Yuzhen Zhou
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2169025b77
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turn off dit_layerwise_offload for wan on rocm (#17569)
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2026-01-23 15:22:42 +08:00 |
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4bf06635fc
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[diffusion] multi-platform: support diffusion on amd and fix encoder loading on MI325 (#13760)
Co-authored-by: Sabre Shao <sabre.shao@amd.com>
Co-authored-by: Yusheng (Ethan) Su <yushengsu.thu@gmail.com>
Co-authored-by: Hubert Lu <Hubert.Lu@amd.com>
Co-authored-by: xsun <sunxiao04@gmail.com>
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2025-12-19 15:38:46 +08:00 |
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Yuzhen Zhou
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0380ca82ef
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Add Batch‑Invariant RMSNorm (#12144)
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2025-10-28 21:05:57 -07:00 |
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