Commit Graph
12929 Commits
Author SHA1 Message Date
5a6a1bb883 [mxfp8-kv] Skip writes to the reserved CUDA-graph padding slot (#35351)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
2026-09-22 01:21:25 +08:00
Liangsheng Yin 800613a74b [Test] Split the serving perf tests by topic into basic_perf/ and route their thresholds through a kit (#40505) 2026-09-21 10:05:57 -07:00
Sage 14e9c40a72 [Observability] Expose python/rust frontend identity in /server_info (#39993)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
2026-09-21 23:32:52 +08:00
hanwlax 8faa2d6731 [NPU][Diffusion] Disable loading latency checks in Ascend fixtures (#40544) 2026-09-21 16:56:35 +08:00
Mohammad Miadh AngkadandMohammad Angkad 8d08dfdab7 [Fix] Add gigachat35 to the tool-call and reasoning parser name lists (#40554)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
2026-09-21 16:34:43 +08:00
ashwini rathi c2f860af1c [ci][xpu] Record device time in the multimodal_gen perf lane (#39956) 2026-09-21 15:39:29 +08:00
b63f8416b3 [Feature] Gigachat 3.5 support (#29189)
Co-authored-by: Stanislav Petrov <stapetrov@sberbank.ru>
Co-authored-by: Viacheslav Barinov <vvadbarinov@sberbank.ru>
Co-authored-by: Viacheslav <viacheslav.teh@gmail.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
2026-09-21 14:37:55 +08:00
kpjeeja b54d5b7c7b disaggregation: Fix FakeKVSender queue accumulation (#28652)
Signed-off-by: KP, Jeeja <jeeja.kp@intel.com>
2026-09-21 14:27:05 +08:00
skyler-apdx f5f3c38aad [Fix] Preserve YaRN scaling when extending rotary caches (#38786) 2026-09-21 14:14:05 +08:00
AMRUTHA MandMa Mingfei d20cd9d77f [XPU]Enable HiSparse hierarchical sparse KV cache on Intel XPU (#32792)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-09-21 14:07:49 +08:00
Lianmin Zheng 11ecdbf39f Clean up startup logging and streamline log audits (#40526) 2026-09-20 22:28:35 -07:00
ashwini rathi 292e3ccc0c [ci][xpu] Re-seed the wan2_1_t2v_1.3b perf baseline on Arc Pro B60 (#39955) 2026-09-21 13:04:35 +08:00
jianzhao-xu 62ba964848 Fix: post-load staging regression breaks offload meta/sharded_gpu modes (#38779) 2026-09-21 11:19:07 +08:00
Xueshen Liu ab03a8e7eb [Perf] Fork-safe import: no CUDA context at import time, lighter argument parsing (#40201) 2026-09-21 10:48:35 +08:00
zhaozx-cn 176dbcb85d [npu]add chunk gdn kernel and unify ssm state layout for ascend gdn backend (#36187) 2026-09-21 09:51:19 +08:00
WenhaoZhang b912db67ea [diffusion] fix: keep Qwen-Image 2.1 prefix KV per layer under Cache-DiT (#40472) 2026-09-21 08:48:31 +08:00
MickandMick Qian 501b7851e4 [diffusion] CI: guard E2E/loading latency with runner-aware baselines (#39206)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
2026-09-21 08:43:22 +08:00
MickandMick Qian 3a0324fb9b [diffusion] optimization: reduce Qwen-Image 2.1 vae and graph warmup memory (#40481)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
2026-09-21 08:42:02 +08:00
Liangsheng Yin 76a9065bef [Fix] Raise on undelivered embeddings in send_with_url, fix broken tests (#40502) 2026-09-20 17:35:27 -07:00
42875bcd2a fix(modelopt): dispatch NVFP4 MoE on the cached backend, not the live global (#38932)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
2026-09-20 19:28:54 -04:00
Mohammad Miadh Angkadandmmangkad 2fa6b94e34 [Perf] Fuse the glm5_next mHC attn->MLP boundary (#39200)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
2026-09-20 16:20:37 -07:00
ollybbmonster 983e643854 [Feature] support bf16 MoE router and mxfp4 MoE for MiMo V2 (#40448) 2026-09-20 16:13:59 -07:00
luoroger37andHank Han d97aed2c90 Fix TopK v2 fallback when 16-block cluster capacity is zero (#40163)
Co-authored-by: Hank Han <hanhan7630@outlook.com>
2026-09-21 06:41:41 +08:00
f31a7bd45c Use pinned memory for asynchronous sampling metadata transfers (#39777)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
2026-09-20 15:31:31 -07:00
Harmya Bhatt 95521da18d [DeepSeek-V4.1] Bound dense prefill indexer memory (#40217) 2026-09-20 14:43:19 -07:00
c2c3629f2d [Kimi-K3] O(1) expert weight lookup in load_weights (#38805)
Signed-off-by: JinYan Su <751080330@qq.com>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
2026-09-20 14:39:45 -07:00
d229952e25 [Fix] Preserve model runner contracts in prefill CUDA graphs (#35452)
Co-authored-by: Oasis-Git <ayw.sirius19@gmail.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
2026-09-20 13:53:14 -07:00
Khoa Pham b3e4d198af [PD] Bound cached-prefix DCP transfers by pack capacity (#40376) 2026-09-21 01:17:15 +08:00
Jimmy ShongandYangmin Li e97614d10c [Qwen4-Exp] Build the offloaded PLE table on the meta device so --ple-offload-embedding never materialises it on the accelerator (#39928)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
2026-09-20 08:28:25 -07:00
ZY Y 5f017ffabb Update test cases and performance testing framework (#40392) 2026-09-20 22:42:00 +08:00
faceless voidandronnie_zheng 791c7850d0 [Diffusion] Enable shared RMSNorm dispatch for SenseNova-U1 (#39705)
Signed-off-by: syd520zy <529477025@qq.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
2026-09-20 17:08:02 +03:00
HuangJi 2a0cb2f04e [Diffusion][MiniMax-H3] Add SM120 Sage compute for SubBlock sparse attention (#40116) 2026-09-20 16:40:28 +08:00
Shuwen WangandSeokhoon Kang 9f3d275940 [HiCache] Fix sparse hybrid transfer layer IDs (#37870)
Co-authored-by: Seokhoon Kang <sh.kang@postech.ac.kr>
2026-09-20 16:24:24 +08:00
amd-danli103andHAI e54009240a [AMD][DSV4] feat: enable DSpark with fp8 unified_kv on gfx950 (#38901)
Co-authored-by: HAI <hixiao@gmail.com>
2026-09-20 01:16:39 -07:00
Ke Bao a8a4d86be9 Remove swa and mamba radix cache (#40313) 2026-09-20 16:16:27 +08:00
Qiaolin Yu f4c256354c [kimi k3][pd disagg] support pp prefill + dcp decode with dspark (#40045) 2026-09-20 00:15:28 -07:00
99a44c88d4 Add out-of-tree DFlash extension points (#38740)
Co-authored-by: Yuhan Chen <yuhanc@fb.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
2026-09-20 14:54:46 +08:00
Yuxuan ZhangandXinyuan Tong 9f21fbc34b [GLM-5.3-Flash] Reduce KPool planning synchronization and overlap indexer preparation (#39695)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
2026-09-19 23:51:17 -07:00
Yuxuan ZhangandXinyuan Tong c8eb54c41d Fuse GLM-5.3-Flash KDA projections and prefill metadata (#39688)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
2026-09-19 23:46:33 -07:00
chaijiacheng888 2d216a11f8 [Model] Serve DeepSeek-OCR-2 with its official 768px local-crop geometry (#38996) 2026-09-20 14:17:21 +08:00
MickandMick Qian 031bff5dd3 [diffusion] chore: batch qwen-image 2.1 targets and document measured deployment recipes (#40408)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
2026-09-20 13:59:36 +08:00
Sasha Sidorov 59dd2fc734 [2/N] [Kernel] Fuse padding-preserving HiSparse slot translation (#39837) 2026-09-20 12:04:03 +08:00
Mohammad Miadh AngkadandMohammad Angkad df0dc44931 [Fix] Forward SWA prealloc reclaim through the DSV4 HiSparse allocator (#40354)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
2026-09-19 20:27:51 -07:00
huangtingweiandChao Shi 020703923d [PP + HiCache] Add PP Prefetch Tickets for eager cross-stage storage prefetch (#36700)
Co-authored-by: Chao Shi <stepinto@live.com>
2026-09-20 11:19:31 +08:00
113f6f080e [PD] Enter the custom mem pool once when allocating DCP pack buffers (#40284)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
2026-09-19 19:34:58 -07:00
Tri Dao d82d653f96 Enable optimistic prefill for Mamba radix-cache models (#40184) 2026-09-19 19:28:11 -07:00
huangtingweiandZhangheng e9300f643e [Unified Cache][9/N] add opt-in MLA load deduplication for Mooncake Linker (#39565)
Co-authored-by: Zhangheng <hzh0425@apache.org>
2026-09-20 09:56:56 +08:00
AndyLi429andAndyLi429 d903351a66 [NPU][bugfix] update low latency quantization input and update MXFP8 tests (#38831)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
2026-09-20 09:55:30 +08:00
f9c2791460 [diffusion] model: support qwen-image-2.1 (#39983)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
Co-authored-by: BBuf <1182563586@qq.com>
2026-09-20 09:46:09 +08:00
BourneSun0527andEven Zhou d2f291c934 [NPU][DSV4]dsv4 enable cpp (#39820)
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
2026-09-20 09:17:27 +08:00