Commit Graph
15288 Commits
Author SHA1 Message Date
YC Yen-Ching Tseng 14095ef78a [AMD] Disable CUDA IPC multimodal transport on ROCm in MMMU VLM tests (#31342) 2026-07-15 18:42:30 -07:00
Mick d9003dd452 fix: skip unsafe automatic prefill graph capture (#31204) 2026-07-16 09:27:38 +08:00
Serge Panev 1c4892d7bb [Mamba] Fix spec-v2 + extra_buffer crash (guard None mamba_next_track_idx) (#27998) 2026-07-15 18:23:14 -07:00
Brayden ZhongandBrayden Zhong 7647a9d260 Fuse the preprocess kernels of trtllm-gen attention (#29690)
Co-authored-by: Brayden Zhong <brayden.zhong@radixark.ai>
2026-07-15 18:21:34 -07:00
McZyWu 871c648203 [NPU]revert add scoring func for GLM 4.7 Flash (#31388) 2026-07-16 09:16:57 +08:00
Brayden ZhongandBrayden Zhong edb2059139 Support Flashinfer one-sided A2A + CuteDSL MoE for Nemotron Ultra (#28309)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
2026-07-15 18:14:20 -07:00
Brayden ZhongandBrayden Zhong ac23be8d09 Skip MXFP8 autotune on dense GEMM, which causes IMA (#29669)
Co-authored-by: Brayden Zhong <brayden.zhong@radixark.ai>
2026-07-15 18:06:55 -07:00
Brayden ZhongandBrayden Zhong 0b04e9da83 Use fused A GEMM for fc1_latent_proj in NemotronH (#29692)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
2026-07-15 18:05:22 -07:00
Liangsheng Yin 1cc9493747 [Spec] Converge DP-attention spec width scaling onto num_tokens_per_req (#31244) 2026-07-15 17:57:08 -07:00
Po-Han Huang (NVIDIA) 5d004a20c5 Fix FlashInfer A2A top-k ID dtype (#29929) 2026-07-15 17:56:11 -07:00
sglang-botandsglang-bot 34f5691ea1 docs: sync LMSYS SGLang blog cards (#31386)
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
2026-07-16 00:53:19 +00:00
Liangsheng Yin b0b2dfbda1 [Spec] Extract the shared draft() tail into build_eagle_verify_input (#31375) 2026-07-15 15:59:31 -07:00
7a973c03a0 [Bugfix] Stamp capture-time num_tokens_per_req in multi-layer EAGLE; close jit_kernel CI filter gaps (#31367)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
2026-07-15 15:24:32 -07:00
Lewisand百麒 3101c1258c [DSv4] Use BF16 instead of FP32 for indexer score computation (#30012)
Co-authored-by: 百麒 <yaozhong.lyz@alibaba-inc.com>
2026-07-15 15:06:55 -07:00
Jorge António 26cb0fcdda Empty _REQ_TYPES_WITH_OPAQUE_FIELDS on the msgpack IPC path (#29465 Task 4) (#30182) 2026-07-15 14:55:06 -07:00
Michael 67148447a6 [AMD] Register 3 CPU-bound / triton unit + light-integration tests for AMD 1-GPU PR CI (#31088) 2026-07-15 14:36:05 -07:00
karverma-amd ec32590025 feat(moriep): add fp4 combine dtype (SGLANG_MORI_COMBINE_DTYPE=fp4) (#30706) 2026-07-15 14:21:41 -07:00
jacky.cheng e78051a419 [AMD] [Fix] Fix --attention-backend triton work for DeepSeek MLA on MI355 (null-K + decode dispatch + RoPE) (#30355) 2026-07-15 14:19:23 -07:00
Liangsheng Yin e76cc75cfa [CI] Remove nightly registrations redundant with scheduled stage runs (#31371) 2026-07-15 14:12:07 -07:00
Yuhao Yang 5abec3fbf8 Fix MiMo-V2 on Blackwell: FA3 fallback and TP-aware audio weight loading (#31343) 2026-07-15 13:26:27 -07:00
Mohammad Miadh Angkad 18043aec20 [CI] Fix TRTLLM MHA graph metadata test fixture (#31332) 2026-07-15 12:44:51 -07:00
Shaun Kotek ab627e5d75 fix: load the right mtp lm head quantization (#30976) 2026-07-15 12:12:04 -07:00
Xuwei 7e7129acd7 [Bugfix] Release Mamba cache after PP dynamic chunk profiling (#31321) 2026-07-16 02:32:07 +08:00
YAMYandXuwei Li 2d00e20a52 [Disagg][Qwen3.5] Fix heterogeneous attn-TP scatter transfer: GDN conv sub-block slice + GQA replicated-KV head map (#30997)
Co-authored-by: Xuwei Li <lixuwei.xy@gmail.com>
2026-07-16 02:31:37 +08:00
Yuhao Yang dd2e4cdc99 Add Inkling cookbook (#31360) 2026-07-16 02:24:31 +08:00
AuFlowandAuFlow 9d147fdca1 [Multimodal] Support n>1 outputs for GLM-Image generation (#31027)
Co-authored-by: AuFlow <AuFlow@users.noreply.github.com>
2026-07-15 20:55:19 +03:00
Liangsheng Yin dc078ddd2a [Spec] Extract stateless draft prepare helpers into eagle_worker_common (#31257) 2026-07-15 10:54:31 -07:00
Bingxu Chenandntgiang71096 d36e96ce23 [AMD] Enable mamba-extra-buffer for Qwen3.5 on ROCm (#30359)
Co-authored-by: ntgiang71096 <nguyentruonggiang71096@gmail.com>
2026-07-15 10:18:12 -07:00
YC Yen-Ching Tsengandkangwangamd a8b60433c2 [AMD] Fix DSV4 JIT build on rocm (#31131)
Co-authored-by: kangwangamd <kangwang@amd.com>
2026-07-15 09:58:12 -07:00
Andy YeandClaude Fable 5 c879f3da5c [diffusion] rl: support rl rollout for the wan pipeline via a per-request scheduler switch (#30036)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
2026-07-15 22:30:51 +08:00
Jun LiuandXinyuan Tong d2b1243be0 docs: document CUDA crash dump output (#31333)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
2026-07-15 22:18:36 +08:00
495ae9aaa6 Fix Ministral3 accuracy issue by aligning YaRN RoPE scaling with Transformers implementation (#31232)
Co-authored-by: Elizaveta Martirosian <elizaveta.martirosian@gmail.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
2026-07-15 15:23:04 +03:00
Артем Савкинandronnie_zheng 8ed82afcc8 [MoE Refactor] [NPU] Refactor Ascend MoE implementation to reduce code duplication and align with community design (#25663)
Co-authored-by: ronnie_zheng <zl19940307@163.com>
2026-07-15 14:59:42 +03:00
c9b17403e7 Fix image URL response for multiple outputs (#30621)
Co-authored-by: AuFlow <AuFlow@users.noreply.github.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
2026-07-15 14:49:04 +03:00
Mick 947a14d617 feat: unify multimodal feature transport (#30904) 2026-07-15 17:42:38 +08:00
weireweireandweireweire f2c875d1c8 [PD] Route PD server warmup to every DP rank (#30748)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
2026-07-15 15:59:41 +08:00
Mohammad Miadh Angkad 5af670284e [CI] Lower GLM-5.2 NVFP4 MTP speed threshold (#31289) 2026-07-15 00:39:58 -07:00
fbcbe0a986 cookbook(deepseek-v4): add MORI disagg backend for AMD + bump MI355X image (#30651)
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
2026-07-15 07:33:05 +00:00
241937af87 [NPU] Determine the topk norm_type through scoring_func (#31107)
Co-authored-by: iridiumine <42236072+iridiumine@users.noreply.github.com>
Co-authored-by: zhaozx-cn <59479021+zhaozx-cn@users.noreply.github.com>
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
2026-07-15 10:26:44 +03:00
Sam ShleiferandAlex Nails dec0836302 Fix processor config loading for object-storage model paths (#31211)
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
2026-07-15 00:21:31 -07:00
skyandBrayden Zhong 980acd6eca Fix MoE TP allreduce to use NCCL symmetric memory via in-pool output allocation (#29007)
Signed-off-by: wangfakang <fakangwang@gmail.com>
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
2026-07-15 15:06:37 +08:00
Ma Mingfei 41e0b4b369 [CPU] add fused input proj for qwen3.5 (#31171) 2026-07-15 15:06:24 +08:00
Yuan Luoandluoyuan.luo a649b5a9db [KDA] Add FlashInfer SM100 KDA decode + MTP (target_verify) backend (#30113)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
2026-07-15 15:04:20 +08:00
fzyzcjy 1afab30577 Fix bookkeeping fields not encapsulated with real allocations in normal alloc, PD pre-alloc, DFlash and EAGLE (#29432) 2026-07-15 14:52:21 +08:00
fzyzcjy e789ca24a7 Lightweight extract allocation logic from mem_cache/common.py to more clearly show nearly parallel variants (#29431) 2026-07-15 14:49:37 +08:00
fzyzcjy c315df49bb Fix abusing presence of req.req_pool_idx to indicate the presence of req.kv resources (#29430) 2026-07-15 14:48:39 +08:00
fzyzcjy 2d979f1d8c Let the presence of req.kv indicate the existence of owned kv resources (#29429) 2026-07-15 14:47:16 +08:00
fzyzcjy 27256aee5b Let cache backend do not couple with owned committed kv details and avoid kv_committed_freed/kv_overallocated_freed fields (#29428) 2026-07-15 14:43:10 +08:00
fzyzcjy d8d76c4d12 Introduce req.kv container for coupled owned kv field lifecycle (#29427) 2026-07-15 14:40:38 +08:00
fzyzcjy 201ddeaba1 Avoid relaying per-step outputs through ScheduleBatch fields in disagg prefill and PP (#30677) 2026-07-15 14:33:37 +08:00