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3a0f1a1344
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[NPU] fix: reach torch>=2.8 CUDA memory-pool APIs lazily via torch._C (#29100)
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-08-29 15:55:14 -07:00 |
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6afb5e1771
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Gate the idle-loop tree-cache sanity check behind a default-off env (#36205)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: hzh0425 <hzh0425@apache.org>
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2026-08-30 00:10:28 +08:00 |
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HZYandZhangheng
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cdbfe90b4a
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[HiCache] Align chunked CUDA host registrations (#36798)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-08-29 20:36:12 +08:00 |
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Cheng WanandClaude Opus 5
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4d53767b09
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config: the lazy imports that buy nothing become eager (#36975)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-29 04:21:54 -07:00 |
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Cheng WanandClaude Opus 5
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f0d621cfa6
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config: the dead record parameters go (#36974)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-29 04:20:55 -07:00 |
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Cheng WanandClaude Opus 5
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1a3e152f03
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config: six more runtime readers ask the bags (#36973)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-29 04:19:14 -07:00 |
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Cheng WanandClaude Opus 5
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b65e677e48
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config: the resolution callbacks into the record go to zero (#36972)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-29 04:18:05 -07:00 |
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Cheng WanandClaude Opus 5
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48b88e1256
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config: the resolution pipeline's dispatcher leaves the record (#36896)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-29 04:16:25 -07:00 |
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Joe RowellandJimmy Shong
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46ccd7ce3e
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Add Laguna-XS-2.1 / S-2.1 NVFP4 nightly gsm8k tests (#35547)
Signed-off-by: Joe Rowell <joe@poolside.ai>
Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com>
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2026-08-29 03:34:46 -07:00 |
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Zhiqiang Xie
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a328c19c81
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[HiCache] buffer mode: decide staged-fetch fate against the live tree (#36834)
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2026-08-29 01:51:47 -07:00 |
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Joel Gustafsonandmmangkad
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0a585d5bb1
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[BugFix] Allow model_loader_extra_config with remote_instance + modelexpress backend (#34639)
Signed-off-by: joeltg <joel@reflection.ai>
Co-authored-by: mmangkad <176301910+mmangkad@users.noreply.github.com>
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2026-08-29 00:43:10 -07:00 |
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Liangsheng Yin
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24a3a63e6b
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[misc] Keep req.kv non-optional and key KV ownership on req_pool_idx (#36958)
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2026-08-28 23:47:42 -07:00 |
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24c9251ac5
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[AMD][Spec][PD] Enable the PD DSA fused-TopK seed remap on ROCm (#36714)
Co-authored-by: Tianxiao Jiang <tianxiaojiang@Tianxiaos-MacBook-Pro.local>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-08-28 22:34:23 -07:00 |
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Eric Zhang
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3904b309db
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Add configurable HTTP/2 connection window (#36920)
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2026-08-29 13:18:42 +08:00 |
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3760296be8
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[PD] Pack DCP1→DCP-N PD KV transfers into dest-contiguous RDMA blocks (#35762)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-08-28 21:41:30 -07:00 |
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+8
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5f216fc33f
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qwen 3.8 rebase (#35758)
Co-authored-by: cherichy <cherichy@outlook.com>
Co-authored-by: guangyunh-nv <guangyunh@nvidia.com>
Co-authored-by: jiahanc <jiahanc@nvidia.com>
Co-authored-by: jinyangyuan-nvidia <joyuan@nvidia.com>
Co-authored-by: Cheng Hang <chang@nvidia.com>
Co-authored-by: Yicheng Qiang <yqiang@nvidia.com>
Co-authored-by: Sam Li <lsam@nvidia.com>
Co-authored-by: Tom-Zheng <tizheng@nvidia.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: xiaoweiw-nv <xiaoweiw@nvidia.com>
Co-authored-by: Zheng Li <lizheng.cs@zju.edu.cn>
Co-authored-by: yizhang2077 <1109276519@qq.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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2026-08-28 20:41:34 -07:00 |
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Chunyuan WU
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92b0d447b0
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[CPU] Fix wrongly causal-masked bidirectional attention (#35434)
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2026-08-28 19:49:43 -07:00 |
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Aurick Qiao
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7276a30c45
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[Fix] Support LSE on the RadixAttention extra-kwargs graph path (#35453)
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2026-08-28 18:04:00 -07:00 |
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Olga Miroshnichenko
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36afd70f9c
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[ROCm][Bugfix] Use token-level KV indices in the aiter ASM context-prefill gather (#36852)
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2026-08-28 17:17:18 -07:00 |
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valechenandHAI
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4944e50e2c
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[AMD] Add Work-Centric (Lean) Attention: a persistent-CTA decode kernel for long-context serving (#33576)
Signed-off-by: Valerie Chen <valechen@amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-08-28 17:00:44 -07:00 |
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Xiaoyu Zhang
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db6f0a9d53
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Refactor JIT kernel and expert-pack directory layout (#36704)
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2026-08-29 07:41:25 +08:00 |
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Gregory Leleytner
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e1b3bba3cc
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[Kernel] Route large SM90 row/column-scaled FP8 GEMMs to Torch (#34318)
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2026-08-29 07:35:37 +08:00 |
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Xiaoyu Zhang
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96a4dcdde8
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[CI] Slim JIT kernel unit tests (#36887)
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2026-08-29 07:26:49 +08:00 |
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Liangsheng Yin
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60f6d77a98
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[mem_cache] Carry swa_evicted_seqlen into SWARadixCache.cache_unfinished_req (#36909)
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2026-08-28 14:29:27 -07:00 |
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Jonny Kongandjonnykong
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4d78d59e51
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[MoE] Make simulated expert routing support DP>1, and fuse into one triton kernel (#29718)
Co-authored-by: jonnykong <jonnykong@fb.com>
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2026-08-28 14:22:45 -07:00 |
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karverma-amd
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2a96ebf648
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[AMD][DSV4] perf: retune decode split-K heuristic for MI355X (#36094)
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2026-08-28 13:48:41 -07:00 |
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Mohammad Miadh Angkad
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70088aa5db
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Fix KeyError on batch requests whose state is freed before it is read (#36638)
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2026-08-28 12:57:07 -07:00 |
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Zhiqiang Xie
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f611e0c073
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[HiCache] Fence load-back behind the forward stream (#36738)
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2026-08-28 11:12:51 -07:00 |
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Zhiqiang Xie
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c9bba091f8
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[HiCache] Key storage prefetch by the request namespace (#36382)
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2026-08-28 11:12:10 -07:00 |
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Cheng WanandClaude Opus 5
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ef20fab38a
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config: the forwarding slots go; the dispatcher calls the family directly (#36792)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-28 10:26:29 -07:00 |
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Cheng WanandClaude Opus 5
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7bc3204117
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config: three cache and pool readers take the bags (#36791)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-28 10:21:32 -07:00 |
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Cheng WanandClaude Opus 5
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43c63a22ff
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config: the derived parallel widths are computed from the leaves (#36790)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-28 10:18:46 -07:00 |
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Cheng WanandClaude Opus 5
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c2928e86d7
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config: the resolution pipeline moves out of the record (#36789)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-28 10:17:24 -07:00 |
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Chao Shi
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8e04f66a70
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HiCache: avoid unnecessary all-reduce in check_prefetch_progress (#36425)
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2026-08-29 00:52:53 +08:00 |
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McZyWu
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69a49fede8
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fix(kimi-k3): preserve dense ModelSlim MLA weights (#36603)
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2026-08-28 02:15:52 -07:00 |
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Zheng Wengang
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1e6d041f78
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[BugFix][VLM] keep Qwen3-VL MoE inference deepstack order (#34690)
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2026-08-28 17:02:16 +08:00 |
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Zhiqiang Xie
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3785b2d20f
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[HiCache] Reject load-back specs that claim nodes pinned by an in-flight load-back (#35931)
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2026-08-28 01:59:06 -07:00 |
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Xiaoyu Zhang
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eebb99c049
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[diffusion][kernel] avoid 4D scale-shift autotuning (#36521)
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2026-08-28 16:58:19 +08:00 |
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Xiaoyu Zhang
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45424d8434
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[diffusion][kernel] support transposed residual-gate add (#36504)
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2026-08-28 16:54:37 +08:00 |
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Zhiqiang Xie
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1061e34785
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[HiCache] Retry L3 storage prefetch after a missed attempt (#36227)
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2026-08-28 01:35:21 -07:00 |
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Yikai Zhangandamdpilot-upstream-sync
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d3b972cbf0
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fix(lora): build the MoE LoRA align JIT kernel on ROCm (#36379)
Co-authored-by: amdpilot-upstream-sync <amdpilot-upstream-sync@users.noreply.github.com>
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2026-08-28 01:18:42 -07:00 |
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Bingxu Chen
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2a7fb511c9
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[AMD][CI] Limit HiCache MGSM eval concurrency on ROCm (#36308)
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2026-08-28 01:05:59 -07:00 |
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Thomas Wang
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baf09f3954
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[AMD] Enable deepseek-v4 topk_transform v2 kernel (#36684)
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2026-08-27 22:36:11 -07:00 |
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Xinyuan Tong
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0665102ce5
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[Fix] Resolve tool argument types through top-level anyOf/oneOf/allOf (#36626)
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2026-08-27 21:50:30 -07:00 |
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2380121e9b
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[HiCache] Stop populating host-pool mmaps twice (-13% allocation time) (#36705)
Co-authored-by: DellCurry <30748980+DellCurry@users.noreply.github.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-28 11:54:11 +08:00 |
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karverma-amd
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2b209711d8
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[AMD][DSV4] perf: MXFP8 MoRI dispatch to match the w4a8 MoE input format (#36119)
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2026-08-27 20:45:40 -07:00 |
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YAMY
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6480cce9bc
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perf: skip redundant scheduler metadata gather for DP1 (#36568)
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2026-08-27 20:04:54 -07:00 |
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Liangsheng Yin
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daf6317196
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[mem_cache] Add free_full to release the full side of a tombstoned SWA node (#36637)
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2026-08-27 19:34:48 -07:00 |
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pllimax
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22f37d414b
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[NPU] Chain PR test jobs and disable two DeepSeek-V4-Flash perf tests (#36672)
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2026-08-28 09:16:09 +08:00 |
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Xiaoyu Zhang
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96b31770f9
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[diffusion] fuse Helios paired transposed RoPE (#36502)
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2026-08-28 08:57:37 +08:00 |
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