Xiaoyu Zhang
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fcb9f229b3
|
[KDA-Pilot] Add LTX2 QKNorm split-RoPE CUDA fast path (#29708)
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2026-07-01 14:42:07 +08:00 |
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Chang Min Bark
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41779d56fd
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fix: make write_token dynamic (#29271)
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2026-06-30 22:55:57 -07:00 |
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Tai An
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546d6e23ad
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fix(mlx): default prefill_aware_swa=False on MlxModelRunnerStub (#29681)
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2026-06-30 22:55:43 -07:00 |
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Lijuan Tang
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3cdc2415b1
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[MLX] Fix step-bounded profiling for bench tools on Apple Silicon (#29217)
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2026-06-30 22:55:29 -07:00 |
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qinsir5522
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a7390b17f8
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[NPU]Modify --lora-backend & --moe-runner-backend description. (#29793)
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2026-07-01 11:15:46 +08:00 |
|
  
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5de66d7fbc
|
[EPD][BugFix] Fix encoder health check with global cache TP (#29296)
Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>
Co-authored-by: siyu <liusy58@linux.alibaba.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
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2026-07-01 11:04:03 +08:00 |
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zhangxiaolei
|
56f22cd520
|
Optimize C128 state pool allocation using request state pool (#28612)
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2026-06-30 19:11:29 -07:00 |
|
Shijin Zhang
|
5b76f55d90
|
[Fix]: Inline H2D during CUDA graph capture to avoid stream isolation in Offloader (#29166)
Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
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2026-06-30 17:49:58 -07:00 |
|
 weireweireandweireweire
|
a01afdd526
|
Support real draft tokens to simulated acceptance (#29645)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
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2026-06-30 17:22:05 -07:00 |
|
 
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53c61bd5e6
|
[bug2] skip swa recovery on locked full kv (#29352)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
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2026-06-30 16:07:06 -07:00 |
|
Yuzhen Zhou
|
99b8f36cb1
|
Skip custom all-reduce v2 CUDA graph capture with torch memory saver. (#27948)
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2026-06-30 14:53:29 -07:00 |
|
  
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bb98629157
|
docs(cookbook): add AMD MI300X/MI325X/MI355X support for GLM-5.2 (#28471)
Co-authored-by: Claude Opus 4 (1M context) <noreply@anthropic.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
|
2026-06-30 21:08:51 +00:00 |
|
 sglang-botandsglang-bot
|
081a01c37d
|
docs: sync LMSYS SGLang blog cards (#29307)
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
|
2026-06-30 20:48:10 +00:00 |
|
TzZtzt
|
e721259079
|
typo-fix: correct mooncake package name to "mooncake-transfer-engine" (#25153)
|
2026-06-30 11:54:36 -07:00 |
|
 
|
97fc4dfd73
|
[Doc]Checking and modifying Markdown formatting issues and link validity (#28586)
Signed-off-by: a60124901 <anyuxin4@h-partners.com>
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
|
2026-06-30 20:27:38 +03:00 |
|
 Feng Yaoandispobock
|
1c2523b719
|
[bug1] keep full kv when swa skips leaf data (#29351)
Co-authored-by: ispobock <ispobaoke@gmail.com>
|
2026-07-01 00:51:18 +08:00 |
|
 YC Yen-Ching Tsengandbingxche
|
c70cc96905
|
[AMD] Stop rocm720 pr auto-runs (#29768)
Co-authored-by: bingxche <bingxche@users.noreply.github.com>
|
2026-06-30 23:58:25 +08:00 |
|
 YC Yen-Ching Tsengandbingxche
|
f2756f53f3
|
[AMD] Update AMD local registry address (#29765)
Co-authored-by: bingxche <bingxche@amd.com>
|
2026-06-30 23:40:00 +08:00 |
|
  ![gemini-code-assist[bot]](/assets/img/avatar_default.png) 
|
cf36dca6d4
|
[JIT Kernel] Triton moe fused gate (#25835)
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: ziyi.xu <ziyi.xu@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-06-30 23:26:18 +08:00 |
|
 Yihao WangandClaude Opus 4.8
|
a531d81c19
|
[diffusion][cache-dit] support Krea-2 + run-driven has_separate_cfg (#29688)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-30 08:22:05 -07:00 |
|
Estrella-xx
|
c6a7c98ae4
|
[NPU]GLM-4.7-Flash optimize with fused kernels (#29509)
|
2026-06-30 19:22:19 +08:00 |
|
nvjullin
|
2f730e299f
|
Disable dsr1 prefill cudagraphs by default (#28053)
|
2026-06-30 16:34:44 +08:00 |
|
Stanley Winata
|
a5e6dd3767
|
[AMD] Implement QuarkW4A8MXFp4MoE to support amd/gpt-oss-120b-w-mxfp4-a-fp8 (#27204)
Signed-off-by: Stanley Winata <stanley.winata@amd.com>
|
2026-06-30 01:24:22 -07:00 |
|
   
|
89620b9169
|
[NPU] Support DeepSeek V4 Flash MTP on Ascend (#28980)
Co-authored-by: Kurkur <mccllm@qq.com>
Co-authored-by: gjsheu <gjsheu@163.com>
Co-authored-by: root <root@localhost.localdomain>
Co-authored-by: khalil2ji3mp6 <khalilzhk@gmail.com>
|
2026-06-30 16:22:13 +08:00 |
|
 cctryandcctry
|
4b4b4af583
|
Budget EAGLE/STANDALONE draft KV pool in SWA pool configurators (#29622)
Co-authored-by: cctry <cctry@fb.com>
|
2026-06-30 00:58:33 -07:00 |
|
silencejade
|
ff51acd67b
|
[NPU] Qwen3-VL-8B use split_qkv_rmsnorm_rope for extend (#29627)
|
2026-06-30 15:55:50 +08:00 |
|
Mohammad Miadh Angkad
|
bae78a44da
|
[Deps] Bump transformers to 5.12.1 (#29393)
|
2026-06-30 00:54:01 -07:00 |
|
Thomas Wang
|
f920a37da4
|
[AMD] Copy decode result on forward_stream instead of copy_stream (#29642)
|
2026-06-29 23:53:48 -07:00 |
|
Mohammad Miadh Angkad
|
b6fceaa789
|
[DSA] Use cos_sin_cache for DSA indexer fusion (#29613)
|
2026-06-29 23:49:00 -07:00 |
|
 
|
dbb51c46ac
|
[CI] Migrate JIT tests missed by #29066 to runner_config registration (#29715)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
|
2026-06-29 23:21:14 -07:00 |
|
Zhangheng
|
dad0120c57
|
[HiSparse]: Skip flaky hisparse-nixl ci (#29710)
|
2026-06-30 14:04:34 +08:00 |
|
Baizhou Zhang
|
cc238270b1
|
Update GLM tests to 5.2 and delete redundant tests (#29686)
|
2026-06-29 23:04:26 -07:00 |
|
 
|
b6907d9664
|
docker: install dynamo nightly in the dev image for rapid iteration/testing (#29634)
Co-authored-by: Kangyan Zhou <zky314343421@gmail.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-29 22:58:19 -07:00 |
|
 
|
54e71506b3
|
[AMD][DSV4] Remove per-batch D2H syncs in MTP to avoid bubbles between 2 batches (#29420)
Co-authored-by: amd-danli103 <amd-danli103@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
|
2026-06-29 22:39:59 -07:00 |
|
 yifei wuandXinyuan Tong
|
f41d455f37
|
[Model] Add HrmTextForCausalLM (Hierarchical Reasoning Model - Text) (#27887)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-06-30 13:32:32 +08:00 |
|
YC Yen-Ching Tseng
|
7d9116d9d7
|
Fix test_type_based_dispatcher after TokenizedGenerateReqInput field changes (#29376)
|
2026-06-29 22:22:22 -07:00 |
|
Michael
|
7da4e30d9b
|
[AMD] Register fused_metadata_copy JIT kernel test for AMD nightly CI (#29671)
|
2026-06-29 21:26:11 -07:00 |
|
 Zhaoyi Liandbingxche
|
6bf15aa2b9
|
[AMD]: Enable NIXL PD disaggregation for ROCm(1/n) (#28348)
Co-authored-by: bingxche <bingxche@amd.com>
|
2026-06-29 21:23:09 -07:00 |
|
Mick
|
2068ae7eec
|
[diffusion] chore: document VAE decode parallel group axes (#29364)
|
2026-06-30 12:14:55 +08:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
|
3add35e26d
|
[Diffusion] Reuse shared AlignedVector and tidy jit_kernel/diffusion (#29664)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
|
2026-06-30 11:38:22 +08:00 |
|
Zaili Wang
|
8dbf04fc56
|
Add new Intel SGLang members into CI_permission list (#29700)
|
2026-06-30 11:06:28 +08:00 |
|
Mohammad Miadh Angkad
|
3a72d02415
|
[DSA] Optimize DSA CUDA graph replay metadata generation (#29499)
|
2026-06-29 19:53:23 -07:00 |
|
Mick
|
25b6051c70
|
[diffusion] warmup: default to model sampling resolution (declare Z-Image default) (#29519)
|
2026-06-30 10:32:11 +08:00 |
|
 
|
3e16be2122
|
[CI] Migrate JIT tests to runner config registration (#29066)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-29 19:12:14 -07:00 |
|
Ho-Ren (Jack) Chuang
|
bc8b3ab1f5
|
[Kernel] Add SM90 Q8KV8 FP8 Sparse MLA Prefill JIT Kernel with Tests and Benchmark (#25751)
|
2026-06-30 09:00:11 +08:00 |
|
Ho-Ren (Jack) Chuang
|
a6bc432fd8
|
[Perf][Kernel] Fuse SiLU+Mul into NVFP4 Expert Quantization for CUTLASS MoE (#18612)
|
2026-06-29 16:51:01 -07:00 |
|
 eeechoandAliceChenyy
|
f0bf96390b
|
[SM120] Add FlashInfer sparse MLA decode for DSv4-Flash (#27455)
Co-authored-by: AliceChenyy <alicechenyy@users.noreply.github.com>
|
2026-06-29 16:27:16 -07:00 |
|
Trevor Morris
|
b8c25bfaa7
|
[NVIDIA] Support flashinfer a2a with flashinfer_trtllm_routed moe (#22394)
|
2026-06-29 16:23:58 -07:00 |
|
 Khoa PhamandClaude Opus 4.7
|
6bdecb8206
|
[DeepSeek V3] Reland: run routed experts on main stream in dual-stream MoE (#29463)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
2026-06-29 15:05:01 -07:00 |
|
Xinyuan Tong
|
45314a9fcb
|
[spec] Fix index_share_for_mtp_iteration being a no-op in EAGLE MTP draft (#29654)
|
2026-06-29 14:52:23 -07:00 |
|