 YanbingJiang
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b188a89a5d
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Fix CI xeon test with triton 3.3.1 (#8086)
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2025-07-16 02:12:23 -07:00 |
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YanbingJiangandDiweiSun
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4de0395343
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Add V2-lite model test (#7390)
Co-authored-by: DiweiSun <105627594+DiweiSun@users.noreply.github.com>
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2025-07-03 22:25:50 -07:00 |
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YanbingJiang
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b044400dd3
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Support non-contiguous query input for extend/decode attention (#7462)
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2025-07-02 19:59:45 -07:00 |
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YanbingJiang
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0e05fe8cf4
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Update seed in CPU UTs to avoid flaky failure with single test (#7544)
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2025-06-25 21:25:50 -07:00 |
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094c116f7d
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Update python API of activation, topk, norm and rope and remove vllm dependency (#6614)
Co-authored-by: Wu, Chunyuan <chunyuan.wu@intel.com>
Co-authored-by: jianan-gu <jianan.gu@intel.com>
Co-authored-by: sdp <sdp@gnr799219.jf.intel.com>
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2025-06-17 22:11:50 -07:00 |
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YanbingJiangandmingfeima
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fcde67b016
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CPU: map changes from developing branch in sgl-kernel (#6833)
Co-authored-by: mingfeima <mingfei.ma@intel.com>
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2025-06-10 01:08:15 -07:00 |
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888cb175a6
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Add intel_amx backend for Radix Attention for CPU (#6408)
Co-authored-by: Chunyuan WU <chunyuan.wu@intel.com>
Co-authored-by: Thien Tran <gau.nernst@yahoo.com.sg>
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2025-05-30 21:37:42 -07:00 |
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YanbingJiang
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d8189660a9
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Update sgl-kernel UTs for activation/topk/norm/rope kernels (#6452)
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2025-05-23 02:03:15 -07:00 |
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YanbingJiangandmingfeima
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32cc66efa5
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Update extend/decode attention kernel for CPU in sgl-kernel and add UTs (#6405)
Co-authored-by: mingfeima <mingfei.ma@intel.com>
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2025-05-19 21:23:17 -07:00 |
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