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8a6ab89bf0
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[AMD] Enable Fast Triton Sparse MLA backend (#30575)
Co-authored-by: clintg6 <7388379+clintg6@users.noreply.github.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-10 01:58:00 -07:00 |
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55b4f4f195
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[Test] Add offline Transformers loader compatibility checks (#38336)
Signed-off-by: adarshxs <adarsh.shirawalmath@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
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2026-09-10 01:07:43 -07:00 |
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1b77f498a0
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[NVIDIA] Support flashinfer Mega Moe (#31470)
Co-authored-by: djns99 <40156487+djns99@users.noreply.github.com>
Co-authored-by: 云挚 <ningyunxiao.nyx@antgroup.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-10 00:22:47 -07:00 |
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Brayden ZhongandBrayden Zhong
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c0b790cf7f
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Delete cutlass_mla, non-Marlin GPTQ, AWQ AOT kernel, and Dual Chunk Flash Attention (#32114)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
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2026-09-10 15:12:01 +08:00 |
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YC Yen-Ching Tseng
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6b2e13bcb0
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[AMD] Fix the diffusion perf fixture lookup (#38686)
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2026-09-10 00:07:08 -07:00 |
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Bingxu Chen
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bd922bc39b
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[AMD][CI] Fix UMBP test buffer after MoRI upgrade (#38672)
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2026-09-10 00:02:00 -07:00 |
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Michael
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026e61bd94
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[AMD] Restore AMD CI registrations dropped by #37436 (#38581)
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2026-09-09 23:59:10 -07:00 |
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DAI0818andPo-Han Huang
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03e4c06589
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Fix Qwen3.5 GDN multi-item scoring (#33922)
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-09 22:30:39 -07:00 |
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Cheng Wan
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f1a512c51c
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[Config] msgspec.Struct for the config tier (#38753)
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2026-09-09 19:41:19 -07:00 |
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Cheng Wan
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53dc77ff4e
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[Config] One writer for the declaration stash; no exception to the write seal (#38752)
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2026-09-09 19:22:06 -07:00 |
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fd596a474c
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[XPU][Fix] Pack device-pointer tables as uint64 to avoid 64-bit address overflow (#35051)
Co-authored-by: roopaksrivastav <roopak.srivastava@intel.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-10 10:12:18 +08:00 |
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92d831d3d7
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[AMD] Parallelize aiter spec-decode KV index building over token blocks (#37659)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
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2026-09-09 17:53:53 -07:00 |
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880d6fa64d
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[DSv4] Integrate TRT-LLM DSv4 Attention for SM100/103 (#30805)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-09 17:40:07 -07:00 |
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Zhiqiang Xie
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beaf3d9252
|
[HiCache] Replace skip_lock_node_ids with a segment lock protocol (#36848)
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2026-09-09 14:55:51 -07:00 |
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FrancisandQiaolin-Yu
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a84ffd1326
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feat: add optimized Domino rollout to DFlash V2 (#36899)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
|
2026-09-09 14:12:15 -07:00 |
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Po-Han Huang (NVIDIA)andYAMY
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96d91ef926
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[Model] Support GLM-5.3 Flash NVFP4 loading (#38621)
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
|
2026-09-09 13:51:08 -07:00 |
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bede776c2a
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fix(unified-memory): evict Full KV for Mamba byte shortfalls (#36713)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
|
2026-09-09 13:46:51 -07:00 |
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paulzhang-tm
|
6c1d0b1b29
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Revert "[Spec] Publish the final multi-layer EAGLE shared-read event" (#38041)
|
2026-09-09 13:01:16 -07:00 |
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Alison ShaoandClaude Opus 5
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95a88bfd69
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Relax GSM8K thresholds for the GLM-5.2 DSA-MTP variants (#38725)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
|
2026-09-09 12:46:10 -07:00 |
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Sage
|
8733da8cf4
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[rust-server] Use node-local HTTP ports for DP attention (#34430)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
|
2026-09-10 02:22:44 +08:00 |
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7b791c9534
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[Bugfix] Keep a shared MAX_LEN prefill CUDA graph bucket when the graph captures a DP gather (MegaMoE sparse-DP hang) (#37933)
Co-authored-by: shyeh25 <206795756+shyeh25@users.noreply.github.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
|
2026-09-09 10:52:16 -07:00 |
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pllimax
|
2b1c4e4c85
|
[NPU] Set DEEPEP_HYBRID_DEPLOYMENT=1 for collocated DeepEP test cases (#38667)
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2026-09-10 00:08:07 +08:00 |
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HuangJi
|
ffe98a4279
|
[Diffusion][MiniMax-H3] Add SM90 Sage compute for SubBlock sparse attention (#37982)
|
2026-09-09 20:00:03 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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72d5c5bb73
|
[Kimi-K3] Accept fp32 routing weights in the fused MoE finalize (#38612)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
|
2026-09-09 01:33:39 -07:00 |
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Pranjal Shankhdharandpranjalssh
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35df2fecde
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[Fix] Stamp sequence-parallel state on dummy forward batches (#38564)
Co-authored-by: pranjalssh <pranjalssh@fb.com>
|
2026-09-09 01:03:03 -07:00 |
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Yuhao Yang
|
13469c16d3
|
Store mamba prefix-cache checkpoints at the configured SSM state dtype (#34820)
|
2026-09-09 15:25:57 +08:00 |
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Ankith AverineniandHaiShaw
|
eb42598bdd
|
[AMD][DSV4] Skip the paged SWA page return under the per-request ring (#38571)
Co-authored-by: HaiShaw <hixiao@gmail.com>
|
2026-09-08 21:15:30 -07:00 |
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Xiaoyu Zhang
|
2952c8d5ea
|
[Diffusion] Fuse LongCat Image normalization and modulation (#38530)
|
2026-09-09 11:12:17 +08:00 |
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Jialin Ouyang
|
7a464a7014
|
[Rust TreeCore] Harden runtime and CI parity (#37303)
|
2026-09-09 10:40:22 +08:00 |
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DayuxiaoshuiandXiaoyu Zhang
|
db1de6ff4c
|
[Diffusion] Keep the Wan VAE decoder channels_last and add a Triton NHWC nearest upsample (#38182)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-09 09:31:35 +08:00 |
|
|
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295132c4a5
|
[NPU] Add sparsity-driven KV offload for DeepSeek DSA on Ascend (#33089)
Co-authored-by: itcj <itcj@foxmail.com>
Co-authored-by: chenyh <chenyh18@mail.ustc.edu.cn>
Co-authored-by: hibikid <7514545+hibikid@user.noreply.gitee.com>
Co-authored-by: Chengjie Tang <tangcj@sxu.edu.cn>
Co-authored-by: wangbiao0814 <wangbiao0814@outlook.com>
|
2026-09-09 09:13:22 +08:00 |
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Cheng Wan
|
db272201a2
|
[Config] Retire get_global_server_args, and clear the deprecated flags that have a replacement (#38375)
|
2026-09-08 16:42:12 -07:00 |
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Baizhou Zhang
|
ed183d45ac
|
[CP V1 Deprecation 4/5] Canonicalize prefill CP API names (#36229)
|
2026-09-08 16:03:36 -07:00 |
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|
+3
|
52fecfdf09
|
support qwen 3.8 flash next (#37500)
Co-authored-by: ch-wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: ispobock <26454835+ispobock@users.noreply.github.com>
Co-authored-by: JustinTong0323 <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: samuellees <26428561+samuellees@users.noreply.github.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: yhyang201 <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: yizhang2077 <25844240+yizhang2077@users.noreply.github.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: Shinto C V <cshintov@gmail.com>
Co-authored-by: Julian Huang <huangzhilin.hzl@antgroup.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: yhyang201 <yhyang201@gmail.com>
|
2026-09-08 13:56:21 -07:00 |
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Brayden ZhongandBrayden Zhong
|
30e7a3072d
|
Keep fp32 routing weights in the fp8 block-scale and bf16 trtllm MoE (#33631)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-09-08 08:56:40 -07:00 |
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HZYandZhangheng
|
8a0863c728
|
[HiCache] Add MLA host-dedup primitives (#36800)
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-09-08 23:40:21 +08:00 |
|
|
Liu Ziming
|
beecfda314
|
[observability] Fix missing e2e/decode/inference latency span attributes (#37789)
|
2026-09-08 22:50:55 +08:00 |
|
|
HZY
|
a6b542813f
|
fix(glm-5.2-nvfp4): bound Mooncake synchronous transfer batches (#32758)
|
2026-09-08 22:14:33 +08:00 |
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SovietPowerandXiaoyu Zhang
|
4df5df911b
|
[Scheduler] Add HRRN schedule policy to significantly reduce TTFT (#32911)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-08 22:14:03 +08:00 |
|
|
Po-Han Huang (NVIDIA)
|
5097f9ac95
|
Disable Hopper GLM shared-expert fusion for modelopt_fp4 Marlin (#37325)
|
2026-09-08 06:16:36 -07:00 |
|
|
pllimax
|
2d339ddef1
|
[NPU] Phase A calibration: full GSM8K eval for dp_attention mixed-chunk (#38422)
|
2026-09-08 21:14:48 +08:00 |
|
|
Xiaoyu Zhang
|
554f817948
|
[Diffusion] Optimize LTX-2 QKNorm and split RoPE on Hopper (#38396)
|
2026-09-08 19:05:02 +08:00 |
|
|
amd-danli103
|
141febf329
|
[AMD] fix: use the hardware fp8 e4m3 convert on gfx950 (#37140)
Signed-off-by: amd-danli103 <danli103@amd.com>
|
2026-09-08 03:01:53 -07:00 |
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|
vorapolsiloai
|
7edcdd5ae6
|
[AMD] Skip AITER FP8 ASM prefill when GQA is unsupported (#38467)
|
2026-09-08 02:49:47 -07:00 |
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|
Sage
|
5aab054ec8
|
[rust-server] fix p/d bootstrap across dp listeners (#36234)
|
2026-09-08 13:22:32 +08:00 |
|
|
Shuwen Wang
|
da1c017ae8
|
[CI] test: initialize disable_radix_cache in scheduler stub (#38418)
|
2026-09-08 13:15:47 +08:00 |
|
|
Anupa Sajikumar
|
91a45ea37e
|
[Intel][XPU][LoRA] Enable LoRA on Intel XPU (#30345)
|
2026-09-08 12:46:41 +08:00 |
|
|
Liangsheng Yin
|
28ebede865
|
[mem_cache] Free hybrid SWA pages by one representative per page on page_size > 1 (#38159)
|
2026-09-07 20:15:54 -07:00 |
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|
Liangsheng Yin
|
b23d835048
|
[Scheduler] Unify per-iteration request intake into ingest_requests() (#38389)
|
2026-09-07 20:02:02 -07:00 |
|
|
EdwardXuyandEdwardXuy
|
7d2d6624b1
|
[NPU] Enable L1 prefix cache for Kimi-K3 W4A8 accuracy test (gpqa) (#38125)
Co-authored-by: EdwardXuy <EdwardXuy@users.noreply.github.com>
|
2026-09-08 10:39:58 +08:00 |
|