 eeecho
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b68702be99
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[DSV4] hc-prenorm: fuse the combine step into a Triton kernel (#35118)
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2026-09-01 02:04:05 -07:00 |
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Ziang Li
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5edcd0a445
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[FlashInfer V0.6.18] feat(dsv4): support --dsa-topk-backend flashinfer with fused top-k (#33237)
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2026-09-01 01:18:10 -07:00 |
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Liangsheng Yin
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3484f7f836
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[mem_cache] Add free_kv_row to release a request's kv row by row range (#36721)
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2026-09-01 01:14:43 -07:00 |
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Xiaoyu ZhangandCursor
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1c3ad92438
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[Diffusion] Fuse FLUX.2 ModelOpt FP8 producers and QKV packing (#37162)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-01 16:14:29 +08:00 |
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Mohammad Miadh Angkad
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03b33cbe5d
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[CI] Fix hybrid wrapper test fake missing kv_index_translator (#37374)
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2026-09-01 00:55:05 -07:00 |
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chien-an-chen
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8a191554e3
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[AMD] Enable 12-head MLA aiter fp8 Gluon decode (batched bh16bn128). (#34647)
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2026-08-31 23:47:45 -07:00 |
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Ma Mingfei
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5e79110122
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[Fix][CPU] fix xeon ci failure by test_qwen35_flashinfer_fusion (#37338)
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2026-09-01 14:17:35 +08:00 |
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Liangsheng Yin
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959ca033eb
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refactor(hicache): simplify decode offload state bookkeeping (#37299)
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2026-08-31 23:09:41 -07:00 |
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Mick
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ae2bd5728b
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[vlm] fix: contain multimodal feature transport failures (#37047)
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2026-09-01 13:46:38 +08:00 |
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YAMY
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33ed29a0ee
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test: update hybrid attention runner fixtures (#37345)
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2026-08-31 22:00:50 -07:00 |
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Liangsheng Yin
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3b14f37b74
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[Fix] Use real ReqKvInfo in unit-test req mocks (#37339)
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2026-08-31 20:25:51 -07:00 |
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Yuan Luoandluoyuan.luo
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5b04408784
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[MoE] Add FlashInfer SM90 MXFP4 W4A8 CUTLASS MoE (#34967)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-08-31 20:04:41 -07:00 |
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22337e9c56
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fix(unified-memory): forward the KV-index translator through every wrapper backend (#37307)
Co-authored-by: Caihua Li <caihua.li@bytedance.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-08-31 19:55:21 -07:00 |
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Mohammad Miadh Angkad
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e6f21cdadc
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[Cohere Command-A-Plus] Optimize decode and BCG capture on SM10X (#36624)
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2026-08-31 19:37:47 -07:00 |
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71cee04ebe
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[Diffusion] Optimize Qwen-Image TP collectives and attention (#36680)
Co-authored-by: Mick <mickjagger19@icloud.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-01 10:28:37 +08:00 |
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Martin Hua
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562b661e0e
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[Feature] Megatron LayerNorm sequence parallelism (--enable-layernorm-sp) (#30915)
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2026-08-31 19:27:28 -07:00 |
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f50b4ad7ae
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[DCP] Support decode context parallelism on the trtllm_mla decode path (#33926)
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-08-31 19:19:44 -07:00 |
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Ziang Li
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9a85473a89
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[FlashInfer v0.6.18] add FlashInfer CuTe DSL NVFP4 W4A16 mode (#35120)
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2026-08-31 18:47:30 -07:00 |
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Xiaoyu ZhangandCursor
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175973d834
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[Diffusion] Fuse Qwen-Image residual norm and NVFP4 quantization (#37129)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-01 08:54:10 +08:00 |
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Xiaoyu ZhangandCursor
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079afaffb1
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[Diffusion] Fuse FLUX.2 gated residual normalization on Blackwell (#37112)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-01 08:38:33 +08:00 |
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Xiaoyu ZhangandCursor
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6715debb2a
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[Diffusion] Fuse Qwen-Image FP8 QKV projection and Blackwell epilogue (#37123)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-01 08:34:41 +08:00 |
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Baizhou Zhang
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07c8f7294d
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Bump sgl-deep-gemm to 0.1.7 (#37279)
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2026-08-31 17:16:34 -07:00 |
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ef9e58fd6d
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feat(unified-memory): three sub-pools for mamba + hybrid-SWA models (#35177)
Co-authored-by: Caihua Li <caihua.li@bytedance.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-08-31 15:10:12 -07:00 |
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98cb3535b7
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feat(unified-memory): byte-budget sizing, feasibility floor, and a conservation verifier (#35158)
Co-authored-by: Caihua Li <caihua.li@bytedance.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-08-31 15:09:28 -07:00 |
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961beee9e5
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fix(unified-memory): four boot/correctness fixes on the hybrid model paths (#35154)
Co-authored-by: Caihua Li <caihua.li@bytedance.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-08-31 15:08:43 -07:00 |
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Liangsheng Yin
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2530204502
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[mem_cache] Make release, row-reuse asserts, and presence checks read the KV record (#37167)
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2026-08-31 12:46:15 -07:00 |
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Liangsheng YinandBaizhou Zhang
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95f0f41021
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[CI] Move tests onto the right CI stages (#34074)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
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2026-08-31 12:39:59 -07:00 |
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Lianmin Zheng
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2138494272
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[Rust] Keep sampling and scheduler wire schemas in sync (#37222)
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2026-08-31 12:31:07 -07:00 |
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Lianmin Zheng
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1da86b9801
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[Rust] Split and rename embedded server components (#37220)
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2026-08-31 12:28:43 -07:00 |
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ishandhanani
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cf51650335
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fix(config): retain pre-engine resolution declarations (#37195)
Signed-off-by: Ishan Dhanani <ishandhanani@gmail.com>
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2026-08-31 12:24:29 -07:00 |
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Yuwei AnandClaude Fable 5
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07d84ebd6d
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[2/N][Mixed] Mixed chunk prefill with spec enabled (#36933)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-08-31 10:48:07 -07:00 |
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9cf157c252
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[Radix Cache] Add Rust TreeCore backend with shared parity tests (#32710)
Co-authored-by: alphabetc1 <2508695655@qq.com>
Co-authored-by: ispobock <ispobaoke@gmail.com>
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2026-09-01 00:26:20 +08:00 |
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Xiaoyu Zhang
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52e1c24744
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[Diffusion] Fuse FLUX.2 token concatenation and NVFP4 quantization (#37141)
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2026-08-31 21:33:02 +08:00 |
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Xiaoyu Zhang
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771e613d96
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[Diffusion] Fuse Qwen-Image final adaptive LayerNorm (#37144)
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2026-08-31 18:22:20 +08:00 |
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Xiaoyu ZhangandCursor
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1ed9bfac2c
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[Diffusion] Fuse Qwen-Image FP8 norm and activation quantization (#37156)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-08-31 18:19:42 +08:00 |
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pllimax
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a874b83c2c
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test: re-enable DSV4-Flash W8A8 8p nightly perf cases (#37214)
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2026-08-31 17:20:46 +08:00 |
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pllimax
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63b2adbeac
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[NPU] Fix evalscope accuracy parsing and add glm5_1 aime26 request timeout (#36459)
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2026-08-31 17:19:03 +08:00 |
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6580d5cd9a
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weight cache: key daemon paths by GPU UUID (#36101)
Co-authored-by: siyu <liusy58@linux.alibaba.com>
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
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2026-08-31 01:44:45 -07:00 |
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+1
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3865efc9f7
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[AMD] support gfx1250 on ROCM 10 (#36871)
Co-authored-by: HAI <hixiao@gmail.com>
Co-authored-by: Kao <akao@amd.com>
Co-authored-by: wunhuang <wunhuang@amd.com>
Co-authored-by: Thomas Wang <1am9trash@gmail.com>
Co-authored-by: Xinyi Song <86638975+RolaoDenthu@users.noreply.github.com>
Co-authored-by: Lin, Soga <soga.lin@amd.com>
Co-authored-by: kk <43161300+kkHuang-amd@users.noreply.github.com>
Co-authored-by: Bingxu Chen <bingxche@amd.com>
Co-authored-by: sogalin_codegen <39478626+sogalin@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-08-31 01:19:11 -07:00 |
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Yuan Luoandluoyuan.luo
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712a720c8a
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[KDA] Fused-accept state advance for FlashInfer KDA MTP verify (#33722)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-08-31 16:11:49 +08:00 |
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Cheng Wan
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f61bb7b40a
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[unified-memory] Drop the vacated 'dense' qualifier and the restating comments (#37170)
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2026-08-31 00:54:13 -07:00 |
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8bb776dc48
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feat(unified-memory): read unified pool from attention backends fa3/flashinfer/trtllm_mha/flashmla (#34613)
Co-authored-by: Caihua Li <caihua.li@bytedance.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-08-30 23:58:24 -07:00 |
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29578d5578
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refactor(unified-memory): translate the KV write location once, at ForwardBatch construction (#35245)
Co-authored-by: Caihua Li <caihua.li@bytedance.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-08-30 23:52:14 -07:00 |
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Ziang Li
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4f997a432a
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test: re-enable FlashInfer per-token NVFP4 coverage (#36985)
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2026-08-30 23:44:09 -07:00 |
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Lianmin ZhengandMing Yang
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3ed3326631
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Decouple speculative draft capacity from runtime state (#36897)
Co-authored-by: Ming Yang <minos.future@gmail.com>
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2026-08-30 23:31:25 -07:00 |
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YAMYandgithub-actions[bot]
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b77cac06a9
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[PP] Support prefill CUDA graph proxy tensors (#36248)
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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2026-08-30 23:11:45 -07:00 |
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Zhanghengand晟海
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5d92e60783
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[Unified Cache Linker][3/N]: Add backend-independent linker core (#37151)
Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>
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2026-08-31 14:07:39 +08:00 |
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ashwini rathi
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10b67aa7a1
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xpu: move prefill-only model tests to the nightly-xpu-1-gpu grid (#36814)
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2026-08-31 14:03:48 +08:00 |
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Liangsheng Yin
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3a6ed55999
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[Fix] Shut hicache test servers down gracefully before SIGKILL (#37194)
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2026-08-30 22:45:40 -07:00 |
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Liangsheng Yin
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5d12ad4fd7
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[mem_cache] Move mamba state and retraction_backup into ReqKvInfo (#37164)
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2026-08-30 22:03:01 -07:00 |
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