[mem_cache] Make release, row-reuse asserts, and presence checks read the KV record (#37167)

This commit is contained in:
Liangsheng Yin
2026-08-31 12:46:15 -07:00
committed by GitHub
parent 95f0f41021
commit 2530204502
13 changed files with 28 additions and 48 deletions
@@ -68,7 +68,7 @@ def make_pool_and_req(capacity: int = 64):
)
req = SimpleNamespace(
inflight_middle_chunks=0,
kv=SimpleNamespace(req_pool_idx=None),
kv=ReqKvInfo(),
)
req_pool_idx = pool.alloc([req])[0]
return pool, req, req_pool_idx, allocator
@@ -3,6 +3,7 @@ from types import SimpleNamespace
import torch
from sglang.srt.managers.schedule_batch import ReqKvInfo
from sglang.srt.mem_cache.allocator import TokenToKVPoolAllocator
from sglang.srt.mem_cache.cache_init_params import CacheInitParams
from sglang.srt.mem_cache.common import retraction_backup
@@ -129,9 +130,7 @@ class TestDecodeRetractionBackup(unittest.TestCase):
)
def _admit_req(self, env, num_tokens: int):
req = SimpleNamespace(
rid="request", kv=SimpleNamespace(req_pool_idx=None), seqlen=num_tokens + 1
)
req = SimpleNamespace(rid="request", kv=ReqKvInfo(), seqlen=num_tokens + 1)
self.assertIsNotNone(env.req_to_token_pool.alloc([req]))
source_indices = env.allocator.alloc(num_tokens)
self.assertIsNotNone(source_indices)
@@ -7,6 +7,7 @@ from types import SimpleNamespace
import torch
from sglang.srt.dllm.mixin.scheduler import DllmManager
from sglang.srt.managers.schedule_batch import ReqKvInfo
from sglang.srt.mem_cache.allocation import alloc_for_extend
from sglang.srt.mem_cache.memory_pool import ReqToTokenPool
from sglang.srt.runtime_context import get_context
@@ -63,7 +64,7 @@ def _make_req(rid, prefix, block_size, *, req_pool_idx=None, reuse=False):
prefix_indices=torch.tensor(prefix, dtype=torch.int32),
dllm_incomplete_ids=array("q", range(block_size)) if reuse else array("q"),
inflight_middle_chunks=1 if req_pool_idx is not None else 0,
kv=SimpleNamespace(
kv=ReqKvInfo(
req_pool_idx=req_pool_idx,
kv_committed_len=len(prefix) if req_pool_idx is not None else 0,
kv_allocated_len=(