 Cheng Wan
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b558cc1abb
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feat(short-conv): shared ShortConvAttnBackend for ZAYA1 CCA + LFM2 short conv (#29867)
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2026-07-01 20:08:00 -07:00 |
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iridiumine
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70df09b833
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Fix MambaPool.clear_slots OOM by replacing expand-based tensor allocation with scalar zeroing (#27923)
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2026-07-02 09:26:55 +08:00 |
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Xinyuan TongandAlison Shao
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0c1a0be3b2
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fix(precision): do not promote failed runs to the comparison baseline (#28190)
Co-authored-by: Alison Shao <54658187+alisonshao@users.noreply.github.com>
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2026-07-01 18:19:15 -07:00 |
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Zhaoyi LiandMichael
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a3f6680874
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[AMD]: docker(rocm) bump Mooncake to latest main + enable multi-protocol (#27730)
Co-authored-by: Michael <13900043+michaelzhang-ai@users.noreply.github.com>
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2026-07-01 17:41:46 -07:00 |
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Xinyuan Tong
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cf7c6ac234
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fix(nightly-precision): pin flashinfer allreduce-fusion backend for TP-partial capture contract (#28925)
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2026-07-01 17:26:19 -07:00 |
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Lianmin Zheng
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1a5977d41b
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[chore] Add no-getattr rule; refine no-dataclasses rule (#29871)
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2026-07-01 15:31:34 -07:00 |
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Lianmin Zheng
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76d828a4e8
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Add pranjalssh to CI_PERMISSIONS.json (#29870)
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2026-07-01 14:52:02 -07:00 |
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Ming Yang
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5ae214f18b
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Extract reusable VMM shareable-handle helpers from register_graph_inputs (#29621)
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2026-07-01 14:02:00 -07:00 |
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YAMYandBaizhou Zhang
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c865347b98
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[DeepSeek V4] Enable FlashMLA sparse prefill by default (#29775)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
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2026-07-01 13:50:05 -07:00 |
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Mohammad Miadh Angkad
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8f0d320d31
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[Spec] Enable FlashInfer autotune for spec draft (#29595)
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2026-07-01 13:36:07 -07:00 |
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Cheng Wanandlch1475369
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4a8e76805c
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feat(mem_cache): unified memory pool for hybrid Mamba / SWA models (#29678)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
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2026-07-01 13:21:59 -07:00 |
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Michael
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3adfd0f34b
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[AMD] Register 3 unit mem_cache + utils tests for stage-b-test-1-gpu-small-amd (#29782)
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2026-07-01 12:57:48 -07:00 |
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Michael
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8361561c24
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[AMD] Fix int8 per-token quant Triton portability + register test for AMD nightly CI (#29694)
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2026-07-01 12:56:33 -07:00 |
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Baizhou Zhang
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c312cdd3a7
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Upgrading tvm-ffi/sgl-deep-gemm/tilelang (#29554)
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2026-07-01 12:32:18 -07:00 |
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Zhihao Wang
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779ea4a9b5
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[RL] fix deepseek v4 MXFP8 flashinfer_trtllm_routed MoE weight update (#28676)
Signed-off-by: zhihaow6 <zhihaow6@illinois.edu>
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2026-07-01 12:29:08 -07:00 |
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eb75d990f7
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[Bugfix] compressed-tensors WNA16 MoE: don't assume a "Linear" config group (#29761)
Signed-off-by: Joe Rowell <joerowell4@gmail.com>
Co-authored-by: Jiminator <jimmysh341@gmail.com>
Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com>
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2026-07-01 18:08:09 +00:00 |
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Kangyan-ZhouandClaude Opus 4.8
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30c9801b39
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[disagg] Fix KV-event publisher port collision under pure data parallelism (#29211)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-01 10:57:34 -07:00 |
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Mick
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03b9278da0
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[diffusion] CI: tighten multimodal-gen consistency thresholds (#29824)
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2026-07-02 01:32:51 +08:00 |
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Zhaoyi Liandbingxche
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9bb7de9258
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[AMD][DI][CI] 2/N Add DSV4 DP8/EP8 and MTP MI355X 1P1D nightly recipes (#29784)
Co-authored-by: bingxche <bingxche@amd.com>
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2026-07-01 23:46:48 +08:00 |
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YC Yen-Ching Tseng
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2a6e5c60fe
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[AMD] Rebalance stage-c-large-8-gpu-mi35x partitions to fix 60-min timeout (#29726)
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2026-07-01 08:17:00 -07:00 |
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13dc5f2dc7
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[HiCache][AMD] Add UMBP tiered DRAM + SSD L3 storage backend with hugepage host allocator (#25377)
Co-authored-by: TianDi101 ditian12@amd.com
Co-authored-by: Niko Ma nima@amd.com
Co-authored-by: Wu, Yutong yutong.wu@amd.com
Co-authored-by: figo fizhang@amd.com
Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-07-01 22:21:37 +08:00 |
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Mohammad Miadh Angkad
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a0d9791810
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[CI] Fix fused EH norm CI registration (#29845)
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2026-07-01 21:27:07 +08:00 |
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huangtingwei
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1e80d938ff
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[HiCache]fix draft host pool allocator type (#29823)
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2026-07-01 19:31:16 +08:00 |
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Mick
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79f334b1aa
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[diffusion] CI: add 5090 job (#29791)
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2026-07-01 19:09:43 +08:00 |
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Lukas Humbel
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7d9de81cda
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feat(hicache): Use NIXL path-mode (#27060)
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2026-07-01 02:59:45 -07:00 |
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Mohammad Miadh Angkad
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07ca24372b
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Add fused EH norm for DeepSeek NextN (#29667)
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2026-07-01 02:46:21 -07:00 |
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Daniel Stokes
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8ee200972e
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[fix] Add support for flashinfer MOE A2A to Qwen3 BF16 model path (#26255)
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2026-07-01 01:59:54 -07:00 |
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Baizhou Zhang
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677a11bfa9
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[Doc] Tiny update dsv4 doc (#29827)
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2026-07-01 01:47:35 -07:00 |
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ashwini rathiandSinghal, Shubham
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5134dcdcab
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[Intel XPU] Initially add nightly GSM8K accuracy tests for Llama-3.1-8B (TP=2) and Qwen3-32B (TP=4) (#28908)
Co-authored-by: Singhal, Shubham <shubham.singhal@intel.com>
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2026-07-01 16:27:24 +08:00 |
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Bingxu Chen
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548f505cc5
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[AMD] Cover DeepSeek-R1 MXFP4 TP4 MTP nightly CI (#29290)
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2026-07-01 01:21:17 -07:00 |
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Michael
|
69ce72020a
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[AMD] Register ltx2_ada_values JIT kernel test for AMD nightly CI (#29693)
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2026-07-01 01:13:55 -07:00 |
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Bingxu Chen
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81a472efcc
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[AMD] Update ROCm AITER pin to 9127c94 (#29816)
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2026-07-01 01:09:11 -07:00 |
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huangtingwei
|
5e1ccd9320
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[HiCache] Optimize HiCache hash generation with bulk token byte conversion (#28287)
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2026-07-01 15:44:23 +08:00 |
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|
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df0dfbaa45
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[Kernel] Strengthen kernel shape coverage (#29636)
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-07-01 15:44:20 +08:00 |
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Xiaoyu Zhang
|
8205aa3603
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chore: clean diffusion dead code (#29789)
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2026-07-01 15:42:16 +08:00 |
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YC Yen-Ching Tseng
|
308d89e042
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[AMD] Split qwen3.5 triton DCP test into its own nightly job (#29409)
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2026-07-01 00:39:39 -07:00 |
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Shijin Zhang
|
00e12cebb4
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[Fix]: Defer DSA MLA CP KV gather for fp8 trtllm prefill in PD mode (#29161)
Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
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2026-07-01 00:20:12 -07:00 |
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zhaozx-cn
|
721350656d
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[NPU] Fix glm 4.6v (#29381)
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2026-07-01 15:13:48 +08:00 |
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Jialin Ouyang
|
40594bd381
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[passthrough] engine: zstd request-body decompression + header overrides (#29684)
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2026-06-30 23:48:56 -07:00 |
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Xiaoyu Zhang
|
47ae1241d3
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[CI] Relax ModelOpt NVFP4 diffusion consistency thresholds (#29767)
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2026-07-01 14:45:08 +08:00 |
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Xiaoyu Zhang
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fcb9f229b3
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[KDA-Pilot] Add LTX2 QKNorm split-RoPE CUDA fast path (#29708)
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2026-07-01 14:42:07 +08:00 |
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Chang Min Bark
|
41779d56fd
|
fix: make write_token dynamic (#29271)
|
2026-06-30 22:55:57 -07:00 |
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|
Tai An
|
546d6e23ad
|
fix(mlx): default prefill_aware_swa=False on MlxModelRunnerStub (#29681)
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2026-06-30 22:55:43 -07:00 |
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Lijuan Tang
|
3cdc2415b1
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[MLX] Fix step-bounded profiling for bench tools on Apple Silicon (#29217)
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2026-06-30 22:55:29 -07:00 |
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qinsir5522
|
a7390b17f8
|
[NPU]Modify --lora-backend & --moe-runner-backend description. (#29793)
|
2026-07-01 11:15:46 +08:00 |
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|
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5de66d7fbc
|
[EPD][BugFix] Fix encoder health check with global cache TP (#29296)
Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>
Co-authored-by: siyu <liusy58@linux.alibaba.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
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2026-07-01 11:04:03 +08:00 |
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zhangxiaolei
|
56f22cd520
|
Optimize C128 state pool allocation using request state pool (#28612)
|
2026-06-30 19:11:29 -07:00 |
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Shijin Zhang
|
5b76f55d90
|
[Fix]: Inline H2D during CUDA graph capture to avoid stream isolation in Offloader (#29166)
Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
|
2026-06-30 17:49:58 -07:00 |
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weireweireandweireweire
|
a01afdd526
|
Support real draft tokens to simulated acceptance (#29645)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
|
2026-06-30 17:22:05 -07:00 |
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|
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53c61bd5e6
|
[bug2] skip swa recovery on locked full kv (#29352)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
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2026-06-30 16:07:06 -07:00 |
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