Commit Graph
33 Commits
Author SHA1 Message Date
Polisetty V R K Jyothendra Varma cf35384fe4 [Intel GPU] Add MLA support to Intel XPU Attention backend for Prefill (#35866)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-09-08 10:29:28 +08:00
Polisetty V R K Jyothendra Varma b168f905c8 [Intel GPU] Align XPU toml file for rust support (#31031)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-09-04 14:48:30 +08:00
Polisetty V R K Jyothendra Varma e59a576f03 fix test/manual/test_forward_split_prefill.py UT due to many refactors and design changes (#36617)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-09-03 01:48:55 -07:00
Polisetty V R K Jyothendra Varma df75ec5f77 [Intel GPU] Add rust support to XPU docker images (#35877) 2026-08-31 10:52:57 +08:00
Polisetty V R K Jyothendra Varma 449f0da78f [Intel GPU] DeepSeek V4 15/N: Add silu_and_mul_clamp support to triton fused_moe for XPU (#33808)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-08-09 21:22:05 -07:00
Polisetty V R K Jyothendra VarmaandMa Mingfei d2c405f19d [Intel GPU] DeepSeek V4 8/N: use sgl-kernel implementation of fused_k_norm_rope_flashmla on XPU (#28040)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-08-05 09:28:43 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 319055c191 [Intel GPU] Add XPU Platform support (#31949)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-24 12:49:29 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 2f823a2eee [Intel GPU] calculate free memory based on allocated memory for XPU (#32044)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-24 08:38:52 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 5325cee7ea Bug fix in compress to support XPU (#31541)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-20 09:34:11 +08:00
Polisetty V R K Jyothendra VarmaandRahul Vijayaraghavan 37f94cb7a0 [Intel GPU] DeepSeek V4 13/N: use sgl-kernel implementation of kernels in V2 Compressor to run on XPU (#28439)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
2026-07-17 09:16:04 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 4dddb04325 [Intel GPU] DeepSeek V4 6/N: use sgl-kernel implemetation of flash_mla_with_kvcache on XPU (#27914)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-03 15:59:38 +08:00
e90fec4868 [Intel GPU] DeepSeek V4 10/N : Add sqrtsoftplus support to fused_topk_torch_native (#28048)
Signed-off-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-03 15:59:12 +08:00
790156c98f [Intel GPU] DeepSeek V4 7/N: Support fused_rope_inplace on XPU using triton (#27915)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-02 13:22:20 +08:00
Polisetty V R K Jyothendra Varma d5abafcc1c [Intel GPU] add pytorch profiling support for XPU in bench offline throughput and enhance num steps (#28308)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
2026-06-29 09:10:15 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei dc113e8804 [Intel GPU] DeepSeek V4 3/N: Support hc_split_sinkhorn on XPU using sgl_kernel (#27783)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-06-26 13:57:13 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 5338e44483 [Intel GPU] fix triton-mla attention on XPU by limiting max_kv_splits to 8 which is default (#28646)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-06-24 09:06:13 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 62b3c8e177 [Intel GPU] Guard tvm_ffi import in dsv4 online mtp module under TYPE_CHECKING to fix import error on XPU (#28531)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-06-22 13:56:21 +08:00
Polisetty V R K Jyothendra Varma fbbf559de2 fix bench_one_batch by extending array with array not list (#28732)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-06-21 08:28:41 +08:00
Polisetty V R K Jyothendra Varma d7c8b9ab9f [Intel GPU] Enable fused_experts in fp8.py for quantized models on XPU (#27533)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-06-09 09:22:30 +08:00
Polisetty V R K Jyothendra Varma fd94bd30b8 [Intel GPU] DeepSeek V4 2/N: Fix tvm ffi import (#26118) 2026-05-24 12:59:49 -07:00
Polisetty V R K Jyothendra Varma 80680dc3fe [Intel GPU] 1/N Fix tilelang import in deepseek v4 rope as optional (#25128) 2026-05-22 18:23:18 +08:00
Polisetty V R K Jyothendra VarmaandBrayden Zhong 52d4c697bb Fix fused_moe import for non-NPU devices (#25076)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
2026-05-12 23:05:51 +03:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 50ed01674e fix is_arch_support_pdl function usage (#24600)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-05-09 09:39:34 +08:00
Polisetty V R K Jyothendra Varma 9dfb1d2ebe [Intel GPU] Fix flash_mla_get_workspace_size call in intel_xpu (#24372)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-05-07 13:45:32 +08:00
Polisetty V R K Jyothendra Varma fdfc46f3a5 [Intel GPU] Enable DeepSeek V3.2 inference on XPU (#24356)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-05-05 20:47:40 +08:00
da7f890788 [Intel GPU] Integrate flash_mla_decode in Intel XPU attention backend (#23557)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-05-01 07:21:28 +08:00
Polisetty V R K Jyothendra Varma 214c35b031 [Intel GPU] Update xpu.Dockerfile to python 3.12 version (#23367) 2026-04-23 09:23:52 +08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 7d2c11970c [Intel GPU] Upgrade pytorch xpu version to 2.11 (#21908)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-04-13 13:16:24 +08:00
Polisetty V R K Jyothendra Varma 599cce4d82 [Intel GPU] import flash_attn functions from sgl_kernel only (#22438) 2026-04-10 15:10:00 +08:00
Polisetty V R K Jyothendra Varma f0303fd07e [Intel GPU] Enable DeepSeek R1 inference on XPU (#18461)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-03-29 22:35:59 -07:00
Polisetty V R K Jyothendra Varma b2dd104ade [Intel GPU] Upgrade pytorch xpu version to 2.10 (#20254)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
2026-03-10 18:47:25 -07:00
Polisetty V R K Jyothendra Varma 71e4d3b6bc [Intel GPU] fix import error to run DeepSeek-V2-Lite model with BF16 on XPU (#10858) 2026-01-29 21:53:53 -08:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 858dc80aff [Intel GPU] fix device in DeepseekScalingRotaryEmbedding to run DeepSeek-V2-Lite BF16 on XPU (#10021)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-01-29 21:21:38 -08:00