 ZiruandNiu Ziru
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1da8ac10e1
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Update to the cookbook for XPU-supported models (#33649)
Co-authored-by: Niu Ziru <niuziru@a4bf018d3341.jf.intel.com>
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2026-09-20 20:26:09 -07:00 |
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jacky.chengandChangLiu0709
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a9bb4d7d45
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[AMD] Align Qwen3.5 MI355X HiCache cookbook with kernel / page_first (#39572)
Co-authored-by: ChangLiu0709 <cliu1004@amd.com>
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2026-09-16 11:22:28 +08:00 |
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jacky.cheng
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2f5cc8e33e
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[AMD] Align Qwen3.5 MI355X cookbook with AttnFP8-V2 and HiCache direct / page_first_direct (#39358)
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2026-09-14 12:46:17 +08:00 |
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ChangLiu0709
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7bc4eb3740
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[AMD] Update MI355X MXFP4 HiCache defaults and quick-reduce quantization for Qwen3.5 cookbook (#39104)
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2026-09-12 00:59:32 -07:00 |
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Kedar PotdarandPo-Han Huang
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f4bbf12423
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docs(cookbook): Qwen3.5 FP8 on B200/B300 — trtllm-gen MoE + symm mem (#38374)
Co-authored-by: Po-Han Huang <pohanh@nvidia.com>
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2026-09-08 09:12:49 +08:00 |
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jacky.cheng
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9eee990ce1
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[AMD] cookbook: add HiCache host-DRAM KV tier for Qwen3.5 MXFP4 on MI355X (#36245)
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2026-08-25 12:55:52 +08:00 |
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zijiexiaandClaude Opus 5
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fe8f9d7457
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[Docs] Add --prerelease=allow to cookbook uv install commands (#35920)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-08-21 15:51:48 -07:00 |
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Faradawn Yang
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91144797c5
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Update Qwen3.5 H200 FP8 for AgentX HiCache MTP (#35194)
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2026-08-17 17:12:07 -07:00 |
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Faradawn Yang
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857910bd35
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docs(semianalysis): Update Qwen3.5 B200 NVFP4 MTP config (#34357)
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2026-08-11 16:12:17 -07:00 |
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Faradawn Yang
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115cd7bde1
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docs: update checkpoint to Qwen3.5 NVFP4 V2 for InfX (#32945)
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2026-08-07 15:26:07 -07:00 |
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zijiexiaandClaude Opus 4.8
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b819d2fb5b
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[Docs] Rename docs_new/ to docs/ (#32123)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-08-03 16:51:00 -07:00 |
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