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[AMD] Update MI355X MXFP4 HiCache defaults and quick-reduce quantization for Qwen3.5 cookbook (#39104)

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ChangLiu0709
2026-09-12 00:59:32 -07:00
committed by GitHub
parent 7c195b9151
commit 7bc4eb3740
2 changed files with 9 additions and 9 deletions
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docs/cookbook/autoregressive/Qwen/Qwen3.5.mdx
+3 -3
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@@ -106,7 +106,7 @@ docker pull lmsysorg/sglang:latest
docker pull lmsysorg/sglang-rocm:v0.5.15.post1-rocm720-mi30x-20260715
# Or use Docker (AMD MI355X)
docker pull lmsysorg/sglang-rocm:v0.5.15.post1-rocm720-mi35x-20260715
docker pull lmsysorg/sglang-rocm:v0.5.19-rocm720-mi35x-20260911
```
For the full Docker setup and other installation methods, please refer to the [official SGLang installation guide](../../../docs/get-started/install).
@@ -127,8 +127,8 @@ This section provides deployment configurations optimized for different hardware
- Speculative decoding (MTP) can significantly reduce latency for interactive use cases.
- **H100 / B200 / B300 FP8:** Add `--enable-symm-mem` to enable NCCL symmetric memory for faster collectives and better performance under multi-GPU settings. It only helps when tp > 1, so on B200/B300 it applies to the 397B-A17B FP8 recipe (tp=4); the 122B-A10B and 35B-A3B FP8 recipes are single-GPU there.
- **AMD GPUs (MI300X / MI325X / MI355X):** Use `SGLANG_USE_AITER=1` and `SGLANG_USE_AITER_UNIFIED_ATTN=1` with `--attention-backend aiter`, which requires `--page-size 16` and can also enable `--enable-aiter-allreduce-fusion`. Additionally set `AITER_FLYDSL_FORCE=1` to force the AITER FlyDSL MoE kernels and `SGLANG_MAMBA_SSM_DTYPE=bfloat16` to store the Mamba SSM state in bfloat16 (instead of the default float32). For the **MXFP4 checkpoint on MI355X**, set `ROCM_QUICK_REDUCE_QUANTIZATION=INT8` to route multi-GPU collectives through INT8-quantized ROCm quick all-reduce, and drop `--enable-aiter-allreduce-fusion` (the two are mutually exclusive; quick all-reduce is preferred for this recipe).
- **KV cache offloading (MXFP4 on MI355X):** Selecting **Host DRAM (HiCache)** adds a host-memory tier below the device KV cache, which lets long-context agentic workloads keep more prefix cached and reach higher concurrency than the device KV pool alone allows. It emits `--enable-hierarchical-cache --hicache-ratio 1.5 --hicache-write-policy write_through --hicache-io-backend direct --hicache-mem-layout page_first_direct`. HiCache extends the radix cache, so the generated command drops `--disable-radix-cache` — the two options are mutually exclusive and SGLang rejects them together at startup. `--hicache-ratio 1.5` sizes the host tier at 1.5x the device KV cache, so make sure the node has that much free CPU DRAM per server on top of the model weights. Leave this **Disabled** for fixed-length throughput serving, where the extra host traffic buys nothing.
- **AMD GPUs (MI300X / MI325X / MI355X):** Use `SGLANG_USE_AITER=1` and `SGLANG_USE_AITER_UNIFIED_ATTN=1` with `--attention-backend aiter`, which requires `--page-size 16` and can also enable `--enable-aiter-allreduce-fusion`. Additionally set `AITER_FLYDSL_FORCE=1` to force the AITER FlyDSL MoE kernels and `SGLANG_MAMBA_SSM_DTYPE=bfloat16` to store the Mamba SSM state in bfloat16 (instead of the default float32). For the **MXFP4 checkpoint on MI355X**, set `ROCM_QUICK_REDUCE_QUANTIZATION=INT4` to route multi-GPU collectives through INT4-quantized ROCm quick all-reduce, and drop `--enable-aiter-allreduce-fusion` (the two are mutually exclusive; quick all-reduce is preferred for this recipe).
- **KV cache offloading (MXFP4 on MI355X):** Selecting **Host DRAM (HiCache)** adds a host-memory tier below the device KV cache, which lets long-context agentic workloads keep more prefix cached and reach higher concurrency than the device KV pool alone allows. It emits `--enable-hierarchical-cache --hicache-ratio 1.5 --hicache-write-policy write_through --hicache-io-backend kernel --hicache-mem-layout page_first`. HiCache extends the radix cache, so the generated command drops `--disable-radix-cache` — the two options are mutually exclusive and SGLang rejects them together at startup. `--hicache-ratio 1.5` sizes the host tier at 1.5x the device KV cache, so make sure the node has that much free CPU DRAM per server on top of the model weights. Leave this **Disabled** for fixed-length throughput serving, where the extra host traffic buys nothing.
- **Watchdog timeout:** Increase `--watchdog-timeout` to `1200` or higher for this large model, as weight loading can take significant time.
- **Mamba Radix Cache**: Qwen3.5's hybrid Gated Delta Networks architecture supports two mamba scheduling strategies via `--mamba-radix-cache-strategy`:
- **V1 (`no_buffer`)**: Default. No overlap scheduler, lower memory usage. Required for AMD MI GPUs.
docs/src/snippets/autoregressive/qwen35-deployment.jsx
+6 -6
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@@ -470,8 +470,8 @@ export const Qwen35Deployment = () => {
// All AMD MI GPUs use the AITER unified-attention backend (pair with
// SGLANG_USE_AITER=1 and SGLANG_USE_AITER_UNIFIED_ATTN=1; see cookbook prose),
// which requires --page-size 16. Multi-GPU runs enable AITER allreduce fusion,
// except the MXFP4 MI355X recipe, which uses ROCm INT8 quantized quick
// all-reduce (ROCM_QUICK_REDUCE_QUANTIZATION=INT8) instead.
// except the MXFP4 MI355X recipe, which uses ROCm INT4 quantized quick
// all-reduce (ROCM_QUICK_REDUCE_QUANTIZATION=INT4) instead.
if (amdGpu) {
const amdFp4 = quantization === 'fp4' && hardware === 'mi355x';
let amdEnv = "SGLANG_USE_AITER=1 \\\nSGLANG_USE_AITER_UNIFIED_ATTN=1 \\\nAITER_FLYDSL_FORCE=1 \\\n";
@@ -479,7 +479,7 @@ export const Qwen35Deployment = () => {
amdEnv += "SGLANG_MAMBA_SSM_DTYPE=bfloat16 \\\n";
}
if (amdFp4) {
amdEnv += "ROCM_QUICK_REDUCE_QUANTIZATION=INT8 \\\n";
amdEnv += "ROCM_QUICK_REDUCE_QUANTIZATION=INT4 \\\n";
}
cmd = amdEnv + cmd;
cmd += " \\\n --attention-backend aiter";
@@ -506,7 +506,7 @@ export const Qwen35Deployment = () => {
// FP4-specific backend settings
if (quantization === 'fp4') {
if (hardware === 'mi355x') {
// AMD MXFP4 on MI355X: backend / --page-size 16 and the INT8 quantized
// AMD MXFP4 on MI355X: backend / --page-size 16 and the INT4 quantized
// ROCm quick all-reduce env are emitted by the AMD backend block above
// (this recipe uses quick all-reduce instead of AITER allreduce fusion).
// Add the FP4-specific flags here.
@@ -517,8 +517,8 @@ export const Qwen35Deployment = () => {
cmd += ' \\\n --enable-hierarchical-cache';
cmd += ' \\\n --hicache-ratio 1.5';
cmd += ' \\\n --hicache-write-policy write_through';
cmd += ' \\\n --hicache-io-backend direct';
cmd += ' \\\n --hicache-mem-layout page_first_direct';
cmd += ' \\\n --hicache-io-backend kernel';
cmd += ' \\\n --hicache-mem-layout page_first';
} else {
cmd += ' \\\n --disable-radix-cache';
}