 Ke Bao
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ae3205ba28
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Fail fast on undersized swa pool (#37610)
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2026-09-05 13:40:37 +08:00 |
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Yash AkhauriandXiaoyu Zhang
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756d0e0a85
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[Model] Add K2 Horizon FP8 checkpoint support (#38033)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-05 13:18:26 +08:00 |
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e980c1a2f1
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fix(glm4v): disambiguate mixed image video offsets (#37971)
Co-authored-by: duxin <xinheng.dx@alibaba-inc.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-05 13:16:16 +08:00 |
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Liangsheng Yin
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0454c074b4
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[mem_cache] Clean up unified allocator leftovers (#38103)
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2026-09-04 22:02:50 -07:00 |
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3a770da756
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[Unified Tree] Support Branching-Point Caching for the SWA Component (#34565)
Co-authored-by: alphabetc1 <2508695655@qq.com>
Co-authored-by: Shuwen Wang <47200617+alphabetc1@users.noreply.github.com>
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2026-09-05 12:29:16 +08:00 |
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Po-Han Huang (NVIDIA)
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991368d880
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Fix Muse Glimmer ModelOpt mixed weight mapping (#37510)
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2026-09-04 20:53:55 -07:00 |
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92a4d8b5ee
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Clean logging under --weight-loader-prefetch-checkpoints (#33930)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-09-04 20:05:53 -07:00 |
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Liangsheng Yin
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0645398a32
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[mem_cache] Move the unified-memory allocators into allocator/ and split the composites out (#38072)
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2026-09-04 19:53:15 -07:00 |
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Xiaoyu ZhangandBBuf
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d6e0a8cbf4
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[diffusion] add Helios per-token gated-residual fusion (quality-gated) (#38042)
Co-authored-by: BBuf <bbuf@users.noreply.github.com>
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2026-09-05 10:29:09 +08:00 |
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Niko MaandZhangheng
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f1f2380d2b
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[Unified Cache][6/N]: Add UMBP external linker (#37578)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-05 09:21:43 +08:00 |
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Xiaoyu ZhangandBBuf
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bc727bc4ee
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[FP8] SM120: route FP8 linear to per-tensor (cudnn/nvjet) instead of channelwise cutlass (#38006)
Co-authored-by: BBuf <bbuf@example.com>
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2026-09-05 09:07:13 +08:00 |
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55bf3380e0
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Support Hy4-preview (#36805)
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: alphabetc1 <2508695655@qq.com>
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2026-09-04 18:03:49 -07:00 |
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Xiaoyu Zhang
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85da5457de
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[diffusion] auto-keep video DiT resident on high-memory GPUs (#38001)
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2026-09-05 08:54:09 +08:00 |
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3c2724c48d
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[AMD] Optimize Kimi-K3 Triton MLA prefill on gfx950 (#35770)
Co-authored-by: clintg6 <7388379+clintg6@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
Co-authored-by: kk <43161300+kkHuang-amd@users.noreply.github.com>
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2026-09-04 17:44:30 -07:00 |
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Alex Nails
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a44bb397a9
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[Perf] Vectorize alloc_extend_naive to remove the per-request Python loop (#37938)
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2026-09-04 17:26:25 -07:00 |
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Lianmin Zheng
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613d87becd
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[Memory] Reuse output storage across full prefill CUDA graphs (#38038)
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2026-09-04 17:23:31 -07:00 |
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YAMY
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65f7957142
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fix: gather CP-sharded tokens before TP-sharded dense MLP under prefill CP (#38078)
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2026-09-04 17:14:31 -07:00 |
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Amy Chang
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8a98f11078
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[feature] Add response-level input/output token ids to chat completions via SglExt (#34488)
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2026-09-04 16:45:13 -07:00 |
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PengYuanandMick Qian
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9c254df8cd
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[diffusion] fix: preserve mapped courier tensor lifetime (#37965)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
|
2026-09-05 07:41:47 +08:00 |
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YAMY
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db89f639ef
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[GDN] Amortize ReplaySSM checkpoint materialization (#35544)
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2026-09-04 15:13:20 -07:00 |
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Hanming Lu
|
e3eeabbbfa
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[Profiler] Add SGLANG_PROFILE_BY_STAGE_DECODE_MIN_BS to defer the decode-stage capture (#38067)
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2026-09-04 15:12:55 -07:00 |
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cctry
|
0eff0f7460
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Add num_prealloc_ready_tokens to decode load snapshot (#38065)
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2026-09-04 15:05:57 -07:00 |
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Yongji WuandLianmin Zheng
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fbf8f1dbf6
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[Fix] Coordinate FullCG prefix variants across DP ranks (#37888)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-04 11:29:30 -07:00 |
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Jialin OuyangandPranjal Shankhdhar
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010dc955be
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[Metrics] Export scheduler stage wall time (#37636)
Co-authored-by: Pranjal Shankhdhar <pranjal.ssh@gmail.com>
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2026-09-04 10:45:53 -07:00 |
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YAMY
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07199fa220
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[Performance] Optimize Qwen3.5 GDN prefill projection layouts (#36267)
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2026-09-04 10:32:44 -07:00 |
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Shuwen WangandClaude Fable 5.1
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5cd2a7661d
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fix: reformat cosmos3_edge.py to satisfy ruff-format (#38023)
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-04 23:39:36 +08:00 |
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huangtingweiandZhiqiang Xie
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0d0e2f92be
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[HiCache] Buffer mode support sidecar pool (#37424)
Co-authored-by: Zhiqiang Xie <xiezhq@stanford.edu>
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2026-09-04 23:24:18 +08:00 |
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8b1d8c1703
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[Metrics] Add rolling scheduler utilization counters (#37461)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
Co-authored-by: pranjalssh <pranjalssh@fb.com>
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2026-09-04 08:06:17 -07:00 |
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4349538c02
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[model] add cosmos3 reasoner to llm only inference (#33572)
Signed-off-by: joeltg <joel@reflection.ai>
Signed-off-by: Joe Rowell <joe@poolside.ai>
Co-authored-by: Dawid Majchrowski <dmajchrowski@nvidia.com>
Co-authored-by: Kedi Wu <kediw@nvidia.com>
Co-authored-by: Kedi Wu <31940276+kediwu0331@users.noreply.github.com>
Co-authored-by: Joel Gustafson <joelgustafson@protonmail.com>
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2026-09-04 22:11:58 +08:00 |
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Shuwen Wang
|
19b46863f3
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fix: align write-through pending across tree cores (#37278)
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2026-09-04 22:08:25 +08:00 |
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Mick
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88021b0734
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[diffusion] chore: make nightly performance measurements robust (#37915)
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2026-09-04 22:03:25 +08:00 |
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Lianmin Zheng
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978cc228ca
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[Rust] Bound multimodal media ingress (#37967)
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2026-09-04 05:22:44 -07:00 |
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Shuwen WangandClaude Opus 5
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e4adf63275
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[Fix] Vacuous marker writes in the cache tests, and an undebited Mamba admission slot (#36415)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-04 19:43:17 +08:00 |
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Kevin MiandClaude Fable 5.1
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3b678549c3
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[diffusion] chore: warm up minimax-h3 at the served clip shape (#37945)
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-04 19:18:02 +08:00 |
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Xiaoyu Zhang
|
f3b2725609
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sm120 32GB mem-tier: raise decode cuda-graph max_bs 24->48 + chunked_prefill 2k->4k (#37898)
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2026-09-04 18:47:26 +08:00 |
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12735c2d76
|
[mm] refactor mm code for rust tokenizer manager (#34660)
Co-authored-by: Rain Jiang <rain-jiang@outlook.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
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2026-09-04 03:03:25 -07:00 |
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CSWYF3634076androot
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b42569a0f1
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[Quant][ue8m0 fix] group requant_weight_ue8m0 reduce reserved gpu memory (#31755)
Co-authored-by: root <root@johor-edge-gpu-a17-13.bec-host.baidu.com>
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2026-09-04 10:03:21 +00:00 |
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Lianmin ZhengandShiyan Deng
|
d7f235daca
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[Memory] Retire graph borrow pool before updating static runs (#37966)
Co-authored-by: Shiyan Deng <dsy842974287@meta.com>
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2026-09-04 02:59:52 -07:00 |
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44c786679f
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[sp] Make attention-TP sequence sharding a per-forward batch property (#37546)
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-04 02:11:03 -07:00 |
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67248e04b4
|
[mem_cache] Route hybrid SWA full-side kv-row frees through free_segment (#37876)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
Co-authored-by: Sam Shleifer <sshleifer@gmail.com>
|
2026-09-04 01:48:33 -07:00 |
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karverma-amdandwunhuang
|
dae126d510
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[AMD][DSv4] Fuse inverse-RoPE into the fp8 wo_a quant (stacked on #37423) (#37658)
Co-authored-by: wunhuang <wunhuang@amd.com>
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2026-09-04 00:51:29 -07:00 |
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Ke Baoandadityakamat24
|
0b57847ebf
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Fix mamba radix cache ssm state indexing (#37836)
Co-authored-by: adityakamat24 <adityakamat007@gmail.com>
|
2026-09-04 15:46:33 +08:00 |
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Xiaoyu Zhang
|
01e66a62db
|
[Diffusion] Improve BCG warmup frame-count diagnostics for video models (#37890)
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2026-09-04 15:05:24 +08:00 |
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AMD-yanfeiwangandkk
|
7f89cc5286
|
[AMD] Skip unused TOPK v2 plan kernel on ROCm (#37580)
Co-authored-by: kk <43161300+kkHuang-amd@users.noreply.github.com>
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2026-09-04 00:00:38 -07:00 |
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1bda9694b7
|
[AMD][DSv4] Switch output projection gemm (oproj_a) to fp8 (#37423)
Signed-off-by: Hemanth Acharya <heachary@amd.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: kk <43161300+kkHuang-amd@users.noreply.github.com>
|
2026-09-03 23:56:07 -07:00 |
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Polisetty V R K Jyothendra Varma
|
b168f905c8
|
[Intel GPU] Align XPU toml file for rust support (#31031)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
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2026-09-04 14:48:30 +08:00 |
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Hemanth Acharya
|
31ebd8f437
|
[AMD][DSv4] Fuse the DSv4 FP4 indexer prefill-schedule preamble into one kernel (#37764)
|
2026-09-03 23:44:49 -07:00 |
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Xiaoyu Zhang
|
54c2c99feb
|
[Diffusion] Fuse LingBot per-token gated residual and RMSNorm modulate (#37910)
|
2026-09-04 14:35:13 +08:00 |
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Yu-Yun ChangandHAI
|
cb32dbc9e0
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[AMD] [Kimi-K3] Fuse the KDA input projection into a single GEMM on ROCm (#35176)
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-03 23:30:08 -07:00 |
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72078cd7f5
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[XPU] Support GPT-OSS MXFP4 checkpoints on Intel XPU (#35751)
Co-authored-by: Meng, Hengyu <hengyu.meng@intel.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-04 14:20:28 +08:00 |
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