3 people 67248e04b4 [mem_cache] Route hybrid SWA full-side kv-row frees through free_segment (#37876) ...

Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
Co-authored-by: Sam Shleifer <sshleifer@gmail.com>

2026-09-04 01:48:33 -07:00

..

sglang

[mem_cache] Route hybrid SWA full-side kv-row frees through free_segment (#37876)

2026-09-04 01:48:33 -07:00

MANIFEST.in

[Kernel] Move sgl-kernel under sglang.kernels.aot (#32648)

2026-07-29 17:25:00 +08:00

pyproject_cpu.toml

[CI] Install sgl-eval from PyPI through the test extra (#37504)

2026-09-02 01:45:25 -07:00

pyproject_npu.toml

[CI] Install sgl-eval from PyPI through the test extra (#37504)

2026-09-02 01:45:25 -07:00

pyproject_other.toml

[CI] Install sgl-eval from PyPI through the test extra (#37504)

2026-09-02 01:45:25 -07:00

pyproject_xpu.toml

[Intel GPU] Align XPU toml file for rust support (#31031)

2026-09-04 14:48:30 +08:00

pyproject.toml

[CI] Install sgl-eval from PyPI through the test extra (#37504)

2026-09-02 01:45:25 -07:00

setup.py

[Rust] Rename mem-cache to sglang-radix-tree (#37290)

2026-09-01 03:03:44 -07:00