 amd-danli103andThomas Wang
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d01812d89e
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[AMD] Optimize KIMI-K3 with Triton MLA decode kernel by tuning the stage-1 geometry for gfx950 (#34580)
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-08-17 21:16:14 -07:00 |
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amd-danli103andamd-danli103
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462b6171bd
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[AMD] Fix stale SWA ring buffer on radix prefix reuse for DeepSeek-V4 with unified_kv backend (#30339)
Co-authored-by: amd-danli103 <dan2.li@amd.com>
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2026-07-09 11:28:22 -07:00 |
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54e71506b3
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[AMD][DSV4] Remove per-batch D2H syncs in MTP to avoid bubbles between 2 batches (#29420)
Co-authored-by: amd-danli103 <amd-danli103@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-06-29 22:39:59 -07:00 |
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c4ec39a785
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[AMD] refactor sparse MLA decode kernel for Deepseek V4 triton backend (#28265)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: yichiche@amd.com <jacky.cheng>
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2026-06-15 03:26:59 -07:00 |
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