 Jinyan ChenandJinyan Chen
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301bcf0872
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Add FP4 Indexer for DeepSeek V4 (#26209)
Co-authored-by: Jinyan Chen <jinyanc@nvidia.com>
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2026-06-02 00:14:38 -07:00 |
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Jinyan ChenandJinyan Chen
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e00b43442d
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[jit-kernel] Add CuTe DSL GDN Decode Kernel (#15631)
Co-authored-by: Jinyan Chen <jinyanc@nvidia.com>
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2026-01-18 12:54:36 -08:00 |
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3067b3f050
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[diffusion] chore: improve model info registration and searching strategy (#14281)
Co-authored-by: Jinyan Chen <jinyanc@nvidia.com>
Co-authored-by: Mick <mickjagger19@icloud.com>
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2025-12-02 18:28:59 +08:00 |
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Jinyan ChenandJinyan Chen
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d88ef4a388
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limit sgl-kernel causal conv1d to cuda only (#10648)
Co-authored-by: Jinyan Chen <jinyanc@nvidia.com>
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2025-09-19 16:59:37 -07:00 |
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Jinyan ChenandJinyan Chen
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fc809665fd
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[Performance] qwen3-next improve causal conv1d in prefill phase (#10595)
Co-authored-by: Jinyan Chen <jinyanc@nvidia.com>
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2025-09-18 11:42:49 -07:00 |
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Jinyan ChenandJinyan Chen
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8a828666a3
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Add DeepEP to CI PR Test (#5655)
Co-authored-by: Jinyan Chen <jinyanc@nvidia.com>
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2025-05-06 17:36:03 -07:00 |
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Jinyan Chenandch-wan
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bc3f6db2dd
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[Fix] DeepEP Compatibility with Low Latency (#5068)
Co-authored-by: ch-wan <cwan39@gatech.edu>
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2025-04-08 20:31:31 -07:00 |
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23c764b18a
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[Feature] Support DeepEP Low Latency (#4767)
Co-authored-by: sleepcoo <sleepcoo@gmail.com>
Co-authored-by: laixinn <xielx@shanghaitech.edu.cn>
Co-authored-by: ch-wan <cwan39@gatech.edu>
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2025-04-01 09:23:25 -07:00 |
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f44db16c8e
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[Feature] Integrate DeepEP into SGLang (#4232)
Co-authored-by: Cheng Wan <cwan39@gatech.edu>
Co-authored-by: Xuting Zhou <xutingz@nvidia.com>
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2025-03-19 08:16:31 -07:00 |
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