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Author SHA1 Message Date
ZiruandNiu Ziru 9d0a8d7536 [CPU] Upgrade torch cpu dependencies to version 2.14. (#37939) 
Co-authored-by: Niu Ziru <niuziru@a4bf018d3341.jf.intel.com>
 2026-09-17 14:01:43 +08:00
BingjiaWang 7782a2a1c8 [Benchmark] Limit warmup concurrency in serving benchmark (#39398) 2026-09-16 22:58:10 -07:00
MickandMick Qian c525ed8f02 [diffusion] fix: preserve explicit attention backends during autotune (#39882) 
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
 2026-09-17 13:28:55 +08:00
ashwini rathi f6f69334ba [XPU] Allow the nightly XPU docker build to target a branch or tag (#39796) 2026-09-17 13:23:09 +08:00
Liangsheng Yin 1c4b130bf7 [CI] Unify basic and speculative sanity accuracy checks with MMLU (#39906) 2026-09-16 22:19:05 -07:00
Liangsheng Yin 923e4a56d4 [CI] Fix sanity evaluation and diffusion test suite blockers (#39892) 2026-09-16 21:47:41 -07:00
eeechoClaude Fable 5YAMY1234Yangmin Li
 		25ce8063f7 Pipeline parallelism x speculative decoding (EAGLE/MTP) compatibility (#30775) 
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
 2026-09-16 21:41:54 -07:00
Chetan Kumar VermaandClaude Opus 5 2733afe54e [diffusion] Fix the XPU capability gates that broke the Wan2.2 A14B DiT path (#36825) 
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-17 12:15:07 +08:00
Liangsheng YinandBBuf 464fffbec8 dsv4.1: chat encoding and tool parsing (#39665) 
Co-authored-by: BBuf <1182563586@qq.com>
 2026-09-16 20:49:42 -07:00
Shuwen Wang 33d46376a6 [HiCache] Yield idle scheduler so storage workers can drain (#38504) 2026-09-17 10:56:11 +08:00
Chunan ZengandKevin Mi 241a5b9823 MiniMax-M3: allow shared-experts fusion on ROCm gfx942 and newer (#36576) 
Co-authored-by: Kevin Mi <kevin.mi@radixark.ai>
 2026-09-16 19:55:47 -07:00
Michele PalazziandTeng Ma 329ffc89b9 [Mooncake] Fix silent SSD offload corruption when TP/PP ranks share ssd_offload_path (#31926) 
Signed-off-by: Michele Palazzi <sysdadmin@m1k.cloud>
Co-authored-by: Teng Ma <sima.mt@alibaba-inc.com>
 2026-09-17 10:51:03 +08:00
Meng, HengyuJuan MunetonYangKai0616devan-carlinAshwini RathiRanjan DebnathJuan MunetonAmrutha M
 		84d7604b7e [XPU] weekly simple model enablement 2026/09/14 (#39439) 
Co-authored-by: Juan Muneton <102537701+jmunetong@users.noreply.github.com>
Co-authored-by: YangKai0616 <kai.yang@intel.com>
Co-authored-by: devan-carlin <devan-carlin@users.noreply.github.com>
Co-authored-by: Ashwini Rathi <arathi@habana.ai>
Co-authored-by: Ranjan Debnath <ranjan.debnath@intel.com>
Co-authored-by: Juan Muneton <juan.muneton.gallego@intel.com>
Co-authored-by: Amrutha M <amrutha.m@intel.com>
 2026-09-17 10:43:04 +08:00
Aurick QiaoAurick QiaoKe Bao
 		4793f56835 [HiCache] Keep hybrid transfer layer maps stage-local under PP (#39699) 
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
 2026-09-17 10:18:44 +08:00
Yonghao ZhuangyhzhuangYJYJLee
 		0daa040e48 Support LongBench v2 in one-batch server benchmarks (#39874) 
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: YJYJLee <yejinlee@meta.com>
 2026-09-16 19:16:03 -07:00
qyb233 4fb9b5b5ba feat(hicache): support NPU Mamba states with FIA and async IO (#32500) 2026-09-17 10:12:26 +08:00
Shuwen Wang 4c85172f3a [HiCache] Back up MXFP8 KV scales in the host pool (#39089) 2026-09-17 09:40:26 +08:00
William Hu 0443e3179f fix(kda_prefill): fence shared writes before async proxy reads (#39124) 2026-09-16 18:37:19 -07:00
Xinyi Song 7780882f18 [AMD][bugfix] Fix dsv4 server launch (#39875) 2026-09-16 18:28:02 -07:00
Liangsheng YinBBufYuhao Yang
 		c89c63fa38 dsv4.1: vision tower and image preprocessing (#39668) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
 2026-09-16 18:11:16 -07:00
Liangsheng Yin 408d2334c3 dsv4.1: mHC computation and compensated projections (#39664) 
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
  Co-authored-by: BBuf <1182563586@qq.com>
  Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
 2026-09-16 17:11:55 -07:00
Liangsheng YinBBufYuhao Yang
 		46ae84df15 dsv4.1: Hopper FP8 matmul kernels and tuning (#39657) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
 2026-09-16 16:54:19 -07:00
Liangsheng Yin dc067c7d8c [Fix] Allow closed object schemas in Outlines prevalidation (#39869) 2026-09-16 16:42:17 -07:00
Chunan Zeng d78b35076a [CI] Fix missing elfutils headers in CUDA 13.4 DeepGEMM build (#39855) 2026-09-16 16:41:29 -07:00
Liangsheng YinDarkSharpnessXiaoyu Zhang
 		c2443458e1 dsv4.1: RoPE and FP4 packing kernels (#39656) 
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: BBuf <1182563586@qq.com>
 2026-09-16 16:17:12 -07:00
William Arnoldandishandhanani f45aad44bd [gRPC] Expose native pause status (#37488) 
Co-authored-by: ishandhanani <82981111+ishandhanani@users.noreply.github.com>
 2026-09-16 15:16:52 -07:00
Liangsheng YinDarkSharpnessXiaoyu Zhang
 		35b7589e1a dsv4.1: candidate indexer library (#39671) 
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
 2026-09-16 15:15:18 -07:00
Liangsheng YinBBufClaude Opus 5DarkSharpness
 		13d593b6cf dsv4.1: compression, KV I/O, and metadata kernels (#39652) 
Co-authored-by: BBuf <1182563586@qq.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
 2026-09-16 13:54:07 -07:00
Justin Perlman 869674b3a7 [Fix] Prevalidate JSON Schema support per grammar backend (#37839) 2026-09-16 13:10:15 -07:00
Qiaolin Yu 43390f63f5 [qwen 3.8 next] change the testing model in test_qwen4_exp_models.py (#39662) 2026-09-16 12:47:45 -07:00
Kangyan-ZhouKangyan ZhouClaude Opus 5
 		b02e16a895 [Router] Fleet-wide sampling contract 3/3: splice injection without re-serializing (#39002) 
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-16 09:59:48 -07:00
Kangyan-ZhouKangyan ZhouClaude Opus 5
 		3e03879f68 [Router] Drain readiness before SIGTERM shutdown so k8s deregisters the pod first (#39016) 
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-16 09:59:26 -07:00
Kan Wu 279339f113 [sgl-router] Share model-file discovery for chat formatters (#39485) 2026-09-16 09:36:11 -07:00
Xinyuan Tong f0bf652534 Add Ling-3.0-flash-VL model support (#38526) 2026-09-17 00:19:26 +08:00
cctry 1b78083b42 [PD] Add optional KV transfer checksums (#39500) 2026-09-16 23:53:30 +08:00
AMD-yanfeiwangandDuyi-Wang a813224e78 [ROCm][DSV4] Enable breakable CUDA graph prefill (#37810) 
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
 2026-09-16 08:52:11 -07:00
Kan WuandClaude Fable 5.1 ad94978adf [sgl-router] Rename chat encoder to chat formatter (#39459) 
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
 2026-09-16 08:46:11 -07:00
Ke Bao 5aaa18207c Revert "[CI] Add e2e test for dp-attention local control broadcast" (#39828) 2026-09-16 23:41:50 +08:00
Kan WuandClaude Fable 5.1 e41026f434 [sgl-router] Forward input_ids only for string content; count tokenize errors only when forwardable (#39458) 
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
 2026-09-16 22:49:41 +08:00
ymren cc171fbad0 feat: support custom OTLP trace service name (#35802) 2026-09-16 22:37:42 +08:00
pllimax 00a9a81b67 [NPU][CI] Fail fast and speed up long-running qwen3.6 accuracy cases (#39813) 2026-09-16 20:20:37 +08:00
ShunkangzandZhangheng e7f7447333 [kv-shard 2/4] Sharded pools (#37615) 
Co-authored-by: Zhangheng <hzh0425@apache.org>
 2026-09-16 19:22:23 +08:00
Sam ShleiferSam ShleiferClaude Fable 5.1
 		76e06febab [CI] Add e2e test for dp-attention local control broadcast (#39437) 
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
 2026-09-16 18:11:40 +08:00
Aurick QiaoandAurick Qiao 7b7620774c Fix device context during NIXL backend initialization (#38774) 
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
 2026-09-16 17:59:24 +08:00
inkcherryandDuyi-Wang a3bf25dc62 [AMD] Clamp MORI intranode grid GPUs (#39763) 
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
 2026-09-16 02:13:59 -07:00
+4
Liangsheng YinCheng WanClaude Opus 5CursorDarkSharpnessDarkSharpnessKe BaoKhoa PhamXiaoyu ZhangXiaoyu ZhangYuhao YangYuwei AnZhichen ZengZiyi Xu
 		7d5696b3a1 dsv4.1: communication kernels and wrappers (#39653) 
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: DarkSharpness <76582120+DarkSharpness@users.noreply.github.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: Xiaoyu Zhang <xiaoyu.zhang@radixark.ai>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
Co-authored-by: Zhichen Zeng <zczeng@uw.edu>
Co-authored-by: Ziyi Xu <ziyi.xu@radixark.ai>
 2026-09-16 02:09:40 -07:00
Bingxu Chen 5a0c1e21e9 [AMD] Preserve deterministic inference when Lean Attention is enabled (#37740) 2026-09-16 02:09:08 -07:00
Bingxu Chen 2cbfaefbf9 [AMD] Avoid the FP8 wo_a path when the weight is BF16 (#38453) 
Signed-off-by: bingxche <bingxche@amd.com>
 2026-09-16 01:57:15 -07:00
Jensenandronnie_zheng 5212797880 [NPU] fix npu docker workspace directory (#39732) 
Signed-off-by: xiedeyantu <czjourney@163.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
 2026-09-16 11:51:38 +03:00
Liangsheng YinandBBuf fc5a979f21 [misc] Merge FlashInfer autotune caches across spec workers, pad MXFP4 TP shards, drop dead ngram attrs (#39678) 
Co-authored-by: BBuf <1182563586@qq.com>
 2026-09-16 01:50:29 -07:00