Michael
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7da4e30d9b
|
[AMD] Register fused_metadata_copy JIT kernel test for AMD nightly CI (#29671)
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2026-06-29 21:26:11 -07:00 |
|
 Zhaoyi Liandbingxche
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6bf15aa2b9
|
[AMD]: Enable NIXL PD disaggregation for ROCm(1/n) (#28348)
Co-authored-by: bingxche <bingxche@amd.com>
|
2026-06-29 21:23:09 -07:00 |
|
Mohammad Miadh Angkad
|
3a72d02415
|
[DSA] Optimize DSA CUDA graph replay metadata generation (#29499)
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2026-06-29 19:53:23 -07:00 |
|
 
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3e16be2122
|
[CI] Migrate JIT tests to runner config registration (#29066)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-29 19:12:14 -07:00 |
|
Ho-Ren (Jack) Chuang
|
bc8b3ab1f5
|
[Kernel] Add SM90 Q8KV8 FP8 Sparse MLA Prefill JIT Kernel with Tests and Benchmark (#25751)
|
2026-06-30 09:00:11 +08:00 |
|
Ho-Ren (Jack) Chuang
|
a6bc432fd8
|
[Perf][Kernel] Fuse SiLU+Mul into NVFP4 Expert Quantization for CUTLASS MoE (#18612)
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2026-06-29 16:51:01 -07:00 |
|
 eeechoandAliceChenyy
|
f0bf96390b
|
[SM120] Add FlashInfer sparse MLA decode for DSv4-Flash (#27455)
Co-authored-by: AliceChenyy <alicechenyy@users.noreply.github.com>
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2026-06-29 16:27:16 -07:00 |
|
Trevor Morris
|
b8c25bfaa7
|
[NVIDIA] Support flashinfer a2a with flashinfer_trtllm_routed moe (#22394)
|
2026-06-29 16:23:58 -07:00 |
|
 Cheng Wanandlch1475369
|
fc96edd297
|
feat(mem_cache): page-major (layer-major within a page) KV/state layout (#29533)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
|
2026-06-29 14:49:54 -07:00 |
|
Mohammad Miadh Angkad
|
6c018eb4d1
|
Fix bounded checkpoint prefetching and buffered drop-cache handling (#29156)
|
2026-06-29 21:49:16 +00:00 |
|
Feng Yao
|
e6c15f76f3
|
[optimize] fix swa eviction boundary for unfinished inserts (#29350)
|
2026-06-30 00:19:15 +08:00 |
|
 Jyothirmai KottuandXinyuan Tong
|
473a278dd1
|
model: support nvidia/LocateAnything-3B (#28958)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-06-30 00:16:42 +08:00 |
|
Shangming Cai
|
93926b9a95
|
Add Qwen3 MoE tests for PP compatibility with CP and DP (#29640)
Signed-off-by: Shangming Cai <csmthu@gmail.com>
|
2026-06-29 18:52:03 +08:00 |
|
 danielafrimiandDaniel Afrimi
|
a2b5ce2ed1
|
Add stochastic rounding for FP16 Mamba SSM cache (#26929)
Signed-off-by: Daniel Afrimi <dafrimi@login-lyris01.lyris.clusters.nvidia.com>
Co-authored-by: Daniel Afrimi <dafrimi@login-lyris01.lyris.clusters.nvidia.com>
|
2026-06-29 01:47:09 -07:00 |
|
SSSunzt
|
91cf159696
|
[PP] bugfix: include CP size in PP rank offset (#29571)
|
2026-06-29 16:01:41 +08:00 |
|
 Brayden ZhongandBrayden Zhong
|
c7b9b92d9a
|
Fix CI caused by https://github.com/sgl-project/sglang/pull/29576 (#29596)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-06-28 23:46:18 -07:00 |
|
Liangsheng Yin
|
c0d45cda29
|
[Spec] Add DFLASH basic sanity CI test (#29338)
|
2026-06-28 23:45:05 -07:00 |
|
Yueming Yuan
|
cd91dd0757
|
fix test_weight_checker_comparator assertion and ue8m0 scale unpack (#29623)
|
2026-06-28 23:36:37 -07:00 |
|
Yueming Yuan
|
e1ca92a7fd
|
[weight checker] refactor: add precision branch; allow ULP quant err; used chunked compare (#28974)
|
2026-06-28 18:44:05 -07:00 |
|
Liangsheng Yin
|
909123ddb8
|
[misc] Use --cuda-graph-max-bs-decode in tests, examples, and docs (#29591)
|
2026-06-28 18:38:28 -07:00 |
|
Ma Mingfei
|
3217410cf6
|
[CPU] enable fused_sigmoid_mul on CPU device (#29378)
|
2026-06-29 09:38:04 +08:00 |
|
Liangsheng Yin
|
abaee4664e
|
[dflash] fa3/fa4: device-side page table; drop seq_lens_cpu D2H sync (#29343)
|
2026-06-28 18:06:33 -07:00 |
|
Chao Shi
|
bd2a5db987
|
[HiCache] Detect for double-free in HostKVCache (#29310)
|
2026-06-29 09:02:21 +08:00 |
|
ishandhanani
|
aaa31eb0a1
|
feat: first-class session identity in SGLang (#29436)
|
2026-06-28 07:16:38 -07:00 |
|
Mick
|
643e1cc779
|
fix: fix prefill-aware SWA floor tracking (#29520)
|
2026-06-28 14:18:28 +08:00 |
|
Xinyuan Tong
|
ddc389cf09
|
[minimax-m3] Split 3/4: disagg K-only index-K transfer (#28714)
|
2026-06-28 13:54:42 +08:00 |
|
Mohammad Miadh Angkad
|
ae09b8302f
|
[CI] Fix GB300 DSV4 Pro FP4 nightly (#29502)
|
2026-06-27 21:06:17 -07:00 |
|
 sglang-botandClaude Sonnet 4.6
|
3d922a51fc
|
test: remove multimodal piecewise CUDA graph gate test (#29537)
Co-authored-by: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
|
2026-06-27 19:03:32 -07:00 |
|
 Khoa PhamandCursor
|
da802ddcaf
|
(perf): Shard Kimi-K2.5 Eagle3 draft fc + symm-mem AG (#29223)
Co-authored-by: Cursor <cursoragent@cursor.com>
|
2026-06-27 17:40:32 -07:00 |
|
 
|
073de15053
|
Fuse the DSA (V3.2, GLM-5.x) indexer Q/K paths into single kernels (#27705)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
Co-authored-by: Kaixi <kaiximatteoc@nvidia.com>
|
2026-06-27 14:29:56 -07:00 |
|
 Brayden ZhongandBrayden Zhong
|
e4253b39e2
|
Support JIT fused A GEMM (MLA down projection) and support GLM-5 hidden size, SM120 (#27397)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-06-27 13:32:06 -07:00 |
|
 Xinyuan Tongandhzh0425
|
592f6c849b
|
[minimax-m3] Split 2/4: mem-cache / HiCache / sparse KV pool (#28713)
Co-authored-by: hzh0425 <hzh0425@apache.org>
|
2026-06-28 00:19:38 +08:00 |
|
 Aditya KamatandMick
|
1589603114
|
model: support baidu unlimited-ocr (#29186)
Co-authored-by: Mick <mickjagger19@icloud.com>
|
2026-06-27 23:36:19 +08:00 |
|
 
|
b030b1a5f3
|
hisparse: support NIXL DRAM KV destinations for HiSparse (#27563)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
|
2026-06-27 22:32:29 +08:00 |
|
 
|
c1b5c7e499
|
Fix DeepSeek V4 PP HiCache SWA allocation and layer mapping (#29106)
Co-authored-by: hjzhang <zhanghjzzz@qq.com>
Co-authored-by: hzh0425 <hzh0425@apache.org>
|
2026-06-27 22:19:14 +08:00 |
|
 jonah-bermanandXinyuan Tong
|
2f34dbe372
|
Add native Exa-backed web_search support (#29342)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-06-27 14:41:09 +01:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
|
495f13fa12
|
[KDA-Pilot] Add diffusion residual-gate CUDA fast path for LTX2 (#29361)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
|
2026-06-27 12:59:41 +08:00 |
|
 IvanShan177andClaude Opus 4.8
|
13b5bd962a
|
fix(spec): track current_token in ReasonerGrammarObject (#29102)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-26 16:43:35 -07:00 |
|
Michael
|
c470acde2b
|
[AMD] Register 1 kernel unit test for AMD nightly CI (#29333)
|
2026-06-26 16:06:02 -07:00 |
|
Lianmin Zheng
|
9c3227b689
|
Fix IPv6 wildcard bootstrap address resolution in disagg (#29459)
|
2026-06-26 16:05:36 -07:00 |
|
YC Yen-Ching Tseng
|
5eebb4b2e8
|
[AMD] Fix fused append+remap DeepEP equivalence test on aiter path (#29377)
|
2026-06-26 16:04:20 -07:00 |
|
Jimmy Shong
|
e745b3af22
|
[Fix] compressed-tensors block FP8: requantize weight scales to UE8M0 for DeepGEMM on Blackwell (#28662)
|
2026-06-26 21:41:18 +00:00 |
|
 Rain JiangandLianmin Zheng
|
be1930133a
|
Convert IPC dataclasses to msgspec.Struct with opt-in msgpack transport (#28688)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
|
2026-06-26 12:04:03 -07:00 |
|
 
|
714011a40f
|
[JIT Kernel] Migrate dsv3_router_gemm from AOT sgl-kernel to JIT kernel (#21531)
Co-authored-by: Guohao Shao <shao.gh.98@gmail.com>
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-06-26 11:52:18 -07:00 |
|
Xiaoyu Zhang
|
18b0e5757e
|
[Diffusion] Fuse LTX2 Ada values (#29390)
|
2026-06-26 23:13:15 +08:00 |
|
Yan Ru Pei
|
c0d4d1897c
|
fix: batch BlockRemoved events per radix node (#29265)
|
2026-06-26 16:13:40 +08:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
|
5996b54bd3
|
[KDA-Pilot] Add diffusion causal Conv3D cat-pad CUDA fast path for Cosmos3 (#29281)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
|
2026-06-26 15:06:49 +08:00 |
|
 Yuan Luoandluoyuan.luo
|
a10a24e9a7
|
[GDN][KDA] ReplaySSM buffered output-only decode for Linear Attention (#28451)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
|
2026-06-26 14:17:02 +08:00 |
|
  
|
cfc0a0e0e0
|
Add Intel Quantization Support in SGLang (#18139)
Signed-off-by: Mengni Wang <mengni.wang@intel.com>
Signed-off-by: WeiweiZhang1 <weiwei1.zhang@intel.com>
Co-authored-by: Peng Zhang <aniz1905@gmail.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
Co-authored-by: Weiwei <weiwei1.zhang@intel.com>
|
2026-06-26 09:54:35 +08:00 |
|
 Khoa PhamandClaude Opus 4.7
|
6c92f9f328
|
fix(bench): pass DCP_RANK/DCP_WORLD_SIZE to set_mla_kv_buffer_kernel (#29356)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
|
2026-06-25 18:13:57 -07:00 |
|