Fix DeepSeek V4 PP HiCache SWA allocation and layer mapping (#29106)

Co-authored-by: hjzhang <zhanghjzzz@qq.com>
Co-authored-by: hzh0425 <hzh0425@apache.org>
This commit is contained in:
hjzhang
2026-06-27 22:19:14 +08:00
committed by GitHub
co-authored by hjzhang hzh0425
parent 2f34dbe372
commit c1b5c7e499
5 changed files with 86 additions and 46 deletions
@@ -34,6 +34,8 @@ def _assert_dsv4_decode_cached_tokens(result, history_len, output_len, label):
class TestUnifiedDeepSeekV4FlashHiCache(UnifiedRadixTreeTestMixin, CustomTestCase):
"""DeepSeek V4 Flash FP8 + HiCache + UnifiedRadixCache."""
tp_size = 4
pp_size = 1
hicache_io_backend = "direct"
hicache_mem_layout = "page_first_direct"
max_running_requests = 4
@@ -49,6 +51,43 @@ class TestUnifiedDeepSeekV4FlashHiCache(UnifiedRadixTreeTestMixin, CustomTestCas
def test_multiturn_logprobs_match(self):
pass
@classmethod
def _server_args(cls):
args = [
"--trust-remote-code",
"--tp-size",
str(cls.tp_size),
]
if cls.pp_size != 1:
args += ["--pp-size", str(cls.pp_size)]
args += [
"--attention-backend",
"compressed",
"--page-size",
"256",
"--chunked-prefill-size",
"8192",
"--mem-fraction-static",
"0.9",
"--disable-shared-experts-fusion",
"--enable-hierarchical-cache",
"--hicache-ratio",
"4",
"--hicache-write-policy",
"write_through",
"--hicache-io-backend",
cls.hicache_io_backend,
"--hicache-mem-layout",
cls.hicache_mem_layout,
"--swa-full-tokens-ratio",
"0.25",
"--max-total-tokens",
"20000",
"--max-running-requests",
str(cls.max_running_requests),
]
return args
@classmethod
def setUpClass(cls):
cls.model = DSV4_FLASH_MODEL
@@ -57,35 +96,7 @@ class TestUnifiedDeepSeekV4FlashHiCache(UnifiedRadixTreeTestMixin, CustomTestCas
cls.model,
cls.base_url,
timeout=DSV4_FLASH_LAUNCH_TIMEOUT,
other_args=[
"--trust-remote-code",
"--tp-size",
"4",
"--attention-backend",
"compressed",
"--page-size",
"256",
"--chunked-prefill-size",
"8192",
"--mem-fraction-static",
"0.9",
"--disable-shared-experts-fusion",
"--enable-hierarchical-cache",
"--hicache-ratio",
"4",
"--hicache-write-policy",
"write_through",
"--hicache-io-backend",
cls.hicache_io_backend,
"--hicache-mem-layout",
cls.hicache_mem_layout,
"--swa-full-tokens-ratio",
"0.25",
"--max-total-tokens",
"20000",
"--max-running-requests",
str(cls.max_running_requests),
],
other_args=cls._server_args(),
env={
"SGLANG_DSV4_FP4_EXPERTS": "0",
"SGLANG_ENABLE_UNIFIED_RADIX_TREE": "1",
@@ -0,0 +1,24 @@
import unittest
import test_unified_radix_cache_kl_dsv4 as dsv4_kl
from sglang.test.ci.ci_register import register_cuda_ci
register_cuda_ci(est_time=900, stage="extra-b", runner_config="8-gpu-h200")
class TestUnifiedDeepSeekV4FlashHiCachePP4TP2(
dsv4_kl.TestUnifiedDeepSeekV4FlashHiCache
):
"""DeepSeek V4 Flash FP8 + HiCache + UnifiedRadixCache under PP4 TP2."""
pp_size = 4
tp_size = 2
@unittest.skip("PP4TP2 coverage uses accuracy and cache-hit KL cases.")
def test_multiturn_logprobs_match(self):
pass
if __name__ == "__main__":
unittest.main()