 Kaixi Hou
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5c34b4f1c7
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[NVIDIA] [2/N] Optimize silu_and_mul_scaled_fp4_grouped_quant perf (#9556)
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2025-08-29 17:17:03 -07:00 |
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Kaixi Hou
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e5638573c1
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[NVIDA] [1/N] Nvfp4 Masked Gemm: Add quant op for the flashinfer grouped gemm (#9200)
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2025-08-22 12:19:45 -07:00 |
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Kaixi Hou
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18da2c96ec
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[NVIDIA] Fix trtllm fp4 moe backend when used in MTP (#9384)
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2025-08-21 00:54:01 -07:00 |
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Kaixi Hou
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b4c9f38a76
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[NVIDIA] Fix missing get_col_major_tma_aligned_tensor for Blackwell deepgemm in EpMoE (#8955)
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2025-08-08 01:12:33 -07:00 |
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Kaixi Hou
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6d0646da11
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[NVIDIA] Fix breakage of using trtllm-gen fp8 moe (#8773)
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2025-08-04 16:30:13 -07:00 |
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Kaixi Houandkushanam
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aa4c66b564
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[NVIDIA] Enable Flashinfer MoE blockscale fp8 backend for TP MoE (#8450)
Co-authored-by: kushanam <42385577+kushanam@users.noreply.github.com>
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2025-07-31 19:56:34 -07:00 |
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Kaixi Hou
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134fa43e19
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[NVIDIA] Change to use num_local_experts (#8453)
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2025-07-28 10:38:19 -07:00 |
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Kaixi Hou
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85486b6f6f
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[NVIDIA] Add Flashinfer MoE blockscale fp8 backend (#8036)
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2025-07-27 00:34:41 -07:00 |
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