Commit Graph
18311 Commits
Author SHA1 Message Date
5f17e3a75f [Router] Fleet-wide sampling contract 1/3: the config surface (#39000)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 21:39:06 -07:00
Xinguo ZhuandAKatydid 4678536df6 [CPU] Add fp8_per_tensor_scaled_mm_cpu kernel (#32618)
Co-authored-by: AKatydid <xinguojoe@gmail.com>
2026-09-16 12:31:05 +08:00
Thomas Wang f60652a43e [AMD] Update deepseek-v4 PDI and cache policy setting for agentic workload (#39702) 2026-09-15 21:16:30 -07:00
Xiaoyu Zhang 444b29c932 [Diffusion] Clean up obsolete worker plumbing, dead helpers, and tests (#39293) 2026-09-16 12:11:45 +08:00
Xinyi Song 954bb6804a [AMD][bugfix] Fix DSV4 MTP crash (#39547) 2026-09-15 21:10:23 -07:00
Xiaoyu Zhang 537ac52c5b [SRT] Clean up no-op compiler pass, dead helpers, and migration tests (#39295) 2026-09-16 12:04:21 +08:00
Zhang, Jiejing 6331e43081 [AMD] Prefer HIP Top-K for GLM-5.x on ROCm (#39631) 2026-09-15 20:55:57 -07:00
jacky.chengandChangLiu0709 a9bb4d7d45 [AMD] Align Qwen3.5 MI355X HiCache cookbook with kernel / page_first (#39572)
Co-authored-by: ChangLiu0709 <cliu1004@amd.com>
2026-09-16 11:22:28 +08:00
chx96642264 5f6dd44edc [NPU] [bugfix] Fix undefined require_attn_tp_allgather (#39561) 2026-09-16 11:02:40 +08:00
Mohammad Miadh AngkadandMohammad Angkad 935cbf24ec Accept MXFP8 dispatch in FlashInfer A2A TRT-LLM MoE (#39613)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
2026-09-15 19:23:15 -07:00
Rahul Vijayaraghavan d4ad368ed9 [Intel XPU] Enable fused_moe_triton tuning on XPU and add tuned DeepSeek-OCR-2 configs (#28723) 2026-09-16 10:20:22 +08:00
Cao E f11cd8ab0e [XPU] Use torch scaled_mm for XPU block FP8 linear (#35605) 2026-09-16 10:10:31 +08:00
Yuxingwang-intelandMa Mingfei 2cb51f5d22 [CPU] [Diffusion] Add fused scale-shift and norm kernels for CPU (#33452)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-09-16 10:01:29 +08:00
Zhang, Jiejingandfanxingran f920be4b09 [AMD] GLM-5.2 NextN: cast draft fused MoE to per-channel FP8 (#39155)
Co-authored-by: fanxingran <xingran.fan@amd.com>
2026-09-15 18:56:48 -07:00
7eedd57ab0 [ROCm] Fix EAGLE spec-decode verify silently sampling greedy on HIP (#37134)
Co-authored-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Jiejing Zhang <jiejing.zhang@amd.com>
2026-09-15 18:49:49 -07:00
Liangsheng Yin 2f7d04da5d dsv4.1: Rust extension modules for image preprocessing, KV pool names, and PD bootstrap (#39677) 2026-09-15 18:11:48 -07:00
Jinyan Yi dbd7281b06 fix(npu): fix hybrid KV transfer with PP prefill in PD disaggregation (#38402) 2026-09-16 09:10:17 +08:00
Zhiqiang Xie 4e9e407d37 [HiCache] Label radix-cache metrics per rank and split the "shrunk" prefetch reason (#39280) 2026-09-15 17:54:04 -07:00
Siyuan ChenandYuwei An c9a8fba991 [DSV4][BCG] Optimize the heavy memory use of C4 Indexer when BCG is enabled (#36534)
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
2026-09-15 17:23:11 -07:00
bbef93e22a [Router] Add a KV storage-tier coverage row to the Grafana dashboard (4/4) (#39111)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 17:09:11 -07:00
63845a1bb2 [router] Resolve a wire protocol per worker at registration (#39004)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 16:54:37 -07:00
Liangsheng Yin 0dabef3d30 [misc] Fix tool-call index, graph padded-row count, and prefill-graph input_embeds refresh (#39574) 2026-09-15 16:37:22 -07:00
fb91baedab [Router] Real-GPU e2e coverage for storage-tier-aware cache routing (3/4) (#39110)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 15:48:51 -07:00
Lianmin Zheng b803cfa0c4 Add external multimodal processors to the Rust frontend (#39329) 2026-09-15 15:38:47 -07:00
2929a39927 Use a shared byte budget for unified hybrid-SWA memory (#36729)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
2026-09-15 15:27:00 -07:00
4da5599e93 Fix first-token metadata and reused attention-layer indexing (#39328)
Co-authored-by: Jinghui Zhang <jinghui@meta.com>
Co-authored-by: Lucia Fang <116399278+luccafong@users.noreply.github.com>
2026-09-15 15:22:26 -07:00
08b1922405 fix(gemma4): set lm_head_is_tied for Gemma4UnifiedForConditionalGeneration (#35809)
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
2026-09-15 15:16:39 -07:00
Liangsheng Yin 87c9f78e99 [Fix][PD] Give prefill and decode their own RDMA NICs in disaggregation tests (#39584) 2026-09-15 15:07:42 -07:00
Cheng Wan 406c9c71d8 [Feature] Support BF16 and batch-invariant inference with DeepEP v2 (#38160) 2026-09-15 14:30:50 -07:00
Liangsheng Yin d58342deab [Fix] Release NCCL on scheduler exit and let the ASGI server own shutdown (#39560) 2026-09-15 13:39:15 -07:00
3c48c1e967 [Router] Expose the KV storage-tier stream and tree occupancy on /metrics (2/4) (#39109)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 13:30:05 -07:00
YAMY 24874f90a3 [Test] Fix DeepGEMM batch invariance test output dtype (#39636) 2026-09-15 12:40:28 -07:00
jasonjk-parkandjasonjk 073fdf97cc Generalize auxiliary outputs (#39164)
Co-authored-by: jasonjk <jasonjk@twshared0085.36.lco2.facebook.com>
2026-09-15 12:05:13 -07:00
Zhiqiang Xie 49f540f3c0 [HiCache] Optimize buffer-mode storage existence bookkeeping (#39480) 2026-09-15 10:49:58 -07:00
Zhiqiang Xie 7f5dd19256 [HiCache] Rework the buffer-mode storage prefetch pipeline and retry bookkeeping (#39283) 2026-09-15 10:48:49 -07:00
Bingxu Chen 03ea13a545 [AMD][CI] Consolidate AMD workflows and retire ROCm 7.0 CI (#38632) 2026-09-15 23:45:22 +08:00
Shangming CaiandClaude Opus 5 47a157f257 [CI][Disaggregation] Fix EADDRINUSE flake in test_disaggregation_dwdp_gpt_oss (#39611)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 23:05:05 +08:00
pllimax 1aeeb25e86 [NPU][CI] Scope NPU nightly artifact dirs by image; fix stale glm5_2 case (#39585) 2026-09-15 22:55:53 +08:00
Siyuan ChenandBJWang-ant 832ec39cc0 [Intra-node PD][DSV4] Pack all layers into one batch for INTRA_NODE_NVLINK path (#38984)
Co-authored-by: BJWang-ant <wangbingjia.wbj@ant-intl.com>
2026-09-15 21:08:33 +08:00
Po-Han Huang (NVIDIA) a2a261963f [CI] Fix SWA decode radix cache NIXL import (#39600) 2026-09-15 21:01:05 +08:00
Yoray ZackandPo-Han Huang 1895cabfa8 Fix mooncake scale joiner groups (#38503)
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
2026-09-15 19:07:25 +08:00
Elizaveta Martirosianandronnie_zheng fb01a079a6 [NPU] [CI] Fix multimodal_gen filter leakage and add daily scheduled run (#39411)
Co-authored-by: ronnie_zheng <zl19940307@163.com>
2026-09-15 14:03:11 +03:00
Yuxuan ZhangandXinyuan Tong 17ba2c2e7c Support non-strict GLM47 tool calls with EBNF constraints (#38890)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
2026-09-15 16:41:48 +08:00
Qiaolin Yu 2c0a70960c [qwen 3.8 next] reuse old cuda stream instead of endlessly creating streams (#39474) 2026-09-15 01:36:14 -07:00
Liangsheng Yin 8565b11003 [misc] Trim redundant variants from the 8-gpu-h20 disaggregation test suite (#39544) 2026-09-15 01:24:46 -07:00
4f52c9948b keeping router GEMM in fp32 for deterministic inference (DeepSeek V3/V4) (#38176)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
2026-09-15 16:16:09 +08:00
Beihao ZhouandBrayden Zhong 37ebacb50f [EPLB] Drop defensive getattr for ep_dispatch_algorithm (#31804)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
2026-09-15 16:14:41 +08:00
Bi XueandLianmin Zheng df254b0a11 [profiler] Label draft-runner steps DRAFT and target verify VERIFY in step spans (#38630)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
2026-09-15 00:57:05 -07:00
0e9b6bf8d8 [Router] Extract worker selection into policies::selection (no behavior change) (#39322)
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-15 15:49:31 +08:00
Khoa Pham e4a6b090f4 [CI] Run test_unified_radix_cache_kl_dcp on cutedsl_mla with bf16 KV cache (#39553) 2026-09-15 00:35:01 -07:00