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11970 Commits
Author SHA1 Message Date
Liangsheng Yin 5d52f02f22 [misc] Fold the allocator free-group flag into free_group (#36739) 2026-08-27 16:12:47 -07:00
Vedant V JhaveriandCopilot dc10483592 [Kernel] Add H200 MoE configs for Qwen3.5 and Qwen3.6 (#35374) 
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
 2026-08-27 16:01:22 -07:00
skyandClaude 0132848349 Revert "[Fix] Disable --enable-symm-mem under CUDA graphs on Kimi hybrid models" (#34842) 
Signed-off-by: wangfakang <fakangwang@gmail.com>
Co-authored-by: Claude <noreply@anthropic.com>
 2026-08-27 14:19:27 -07:00
Yuwei AnandClaude Fable 5 ff5578eb4e [1/N][Mix] Mixed Chunk Prefill Base (#36288) 
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
 2026-08-27 12:59:56 -07:00
Cheng WanandClaude Opus 5 6ff2a20ccf config: the record is not an object that gets passed around (#36622) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 12:57:10 -07:00
Cheng WanandClaude Opus 5 fd40a331bf config: a parallel size has one spelling; a patched scope declares its own (#36621) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 12:56:42 -07:00
Cheng WanandClaude Opus 5 ca1d7ed8e6 config: a parallel leaf with no live counterpart is read bare (#36620) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 12:56:11 -07:00
Cheng WanandClaude Opus 5 7c3b5a6732 config: every handler declares its cuda-graph decisions (#36725) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 12:55:34 -07:00
Cheng WanandClaude Opus 5 bd4bb1781a config: resolution declares, and nothing writes a field (#36618) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 12:53:17 -07:00
Lianmin Zheng a0a2295271 Refactor server_args constants and layout (#36676) 2026-08-27 12:16:16 -07:00
Mickandjohn.xh 20a491d1d3 [Fix] Re-encode multimodal embeddings after cache mismatch (#36595) 
Co-authored-by: john.xh <dengxuhuijohn@gmail.com>
 2026-08-27 23:24:30 +08:00
Xiaoyu Zhang 024a7a1031 [diffusion] Fix native LingBot-Video text encoding (#36542) 2026-08-27 22:58:22 +08:00
inkcherry 8ad76415e2 [PD][mori] Align prefill transfer control plane for unified control plane (#36160) 2026-08-27 21:43:13 +08:00
Xiaoyu Zhang a7e3f590ca [Diffusion] Fuse LongCat residual gate updates (#36577) 2026-08-27 21:07:04 +08:00
Xiaoyu Zhang e061dd1b47 [Diffusion][Kernel] Fuse Wan FFN GELU epilogue (#36592) 2026-08-27 21:06:28 +08:00
Xiaoyu Zhang 1af95ffded [diffusion] Fuse Cosmos3 Nano T2I attention on Hopper (#36571) 2026-08-27 20:59:15 +08:00
Xiaoyu Zhang db4125bb56 [diffusion] Accept mesh benchmark artifacts (#36553) 2026-08-27 20:53:25 +08:00
Xiaoyu Zhang d42fa5e10a [diffusion] align video BCG warmup frame count (#36485) 2026-08-27 20:52:00 +08:00
xdtbynd b647ae82f5 [NPU][Bugfix] Fix OOB gather in decode KV allocation when free pool is tight (#35727) 2026-08-27 19:44:45 +08:00
Shangming CaiKangyan ZhouZhangheng
 		97ba99067d Publish per-scheduler load on a dedicated socket for load-aware routers (#34608) 
Co-authored-by: Kangyan Zhou <zky314343421@gmail.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
 2026-08-27 19:33:18 +08:00
Lianmin Zheng 94183a8d2b Move server args config parser under utils (#36681) 2026-08-27 03:34:50 -07:00
Xiaoyu Zhang ad911a5ec0 [kernel] Tune LingBot-Video MoE TMA configs for H100 (#36543) 2026-08-27 02:47:32 -07:00
Schwinn Saereesitthipitak 08315c56df [Fix] Account resident weight memory in KV sizing (#34053) 
Signed-off-by: Schwinn Saereesitthipitak <schwinns@nvidia.com>
 2026-08-27 02:43:04 -07:00
Xia Weiwen 56fdfc3b26 XPU: remove SGLANG_USE_SGL_XPU flag (#34492) 2026-08-27 02:38:02 -07:00
Khoa Pham 78d36f5f62 fix: kill_process_tree waits for the reap by default (#36589) 2026-08-27 02:34:05 -07:00
AMD-yanfeiwang 2ded8a6aea [AMD] Enable moe_a2a_backend=mori for DeepSeek-V4 prefill context parallelism (#35611) 2026-08-27 02:31:41 -07:00
Lianmin Zheng 3402265989 [Core] Refactor server argument choices (#36586) 2026-08-27 01:56:03 -07:00
MickandClaude Opus 5 c2c3320cf0 [VLM] feat: size the multimodal preprocessing pool by where preprocessing runs (#35349) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 16:32:58 +08:00
GoldPancakealphabetc1Shuwen WangClaude Opus 5
 		b8a6adadfe [Bug][Spec] fix startup crash and reduce CUDA graph memory usage for speculative adaptive (#35275) 
Co-authored-by: alphabetc1 <2508695655@qq.com>
Co-authored-by: Shuwen Wang <47200617+alphabetc1@users.noreply.github.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-08-27 00:46:13 -07:00
jacky.cheng c967cd19b5 [AMD] Optimize Qwen3.5 MTP unified attention on gfx950 (#36330) 2026-08-27 00:13:49 -07:00
ashwini rathiClaude Opus 4.7Ma Mingfei
 		72bf8c4d53 [ci] xpu: trigger pr-test-xpu on multimodal_gen changes (#36100) 
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
 2026-08-27 14:50:26 +08:00
Xun Sun adcf73d7f7 [Weight Cache] Enhance test and support EPLB (#36198) 2026-08-26 23:11:53 -07:00
weireweireandweireweire ea48cb04cc Pin scheduler metadata before asynchronous H2D copies (#35944) 
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
 2026-08-26 22:21:47 -07:00
jacky.cheng f775db03aa [AMD] Fix int32 seqused_k overflow in aiter draft-extend attention (#36541) 2026-08-26 22:06:39 -07:00
weireweireandweireweire 4d5d506486 Publish gated DSV4 DFLASH-family target-prefill read completion (#35947) 
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
 2026-08-26 21:33:08 -07:00
Jialin Ouyang a2b589fdf8 [Radix Cache] Add test-only TreeCore inspector for shared backend tests (#35791) 2026-08-27 11:17:51 +08:00
MengYumenyuJinyan ChenHan YuCheng Wan
 		a3ae667d67 [Feature] Add DeepEPv2 (ElasticBuffer) MoE A2A backend (#35634) 
Co-authored-by: menyu <menyu@nvidia.com>
Co-authored-by: Jinyan Chen <93358689+liz-badada@users.noreply.github.com>
Co-authored-by: Han Yu <helloyu0903@gmail.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
 2026-08-26 19:54:33 -07:00
AMD-yanfeiwang cbfe54fba8 [AMD] Use fast exponentials in C4 and C128 ROCm kernels (#34296) 2026-08-26 19:49:01 -07:00
MickandClaude Opus 5 07570202f0 [VLM] route every multimodal processor through the worker pool's call site (#35342) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-08-27 10:27:45 +08:00
Zaili Wang 5adc2880f9 [CPU] Enable ERNIE models on CPU (#35222) 2026-08-27 10:13:10 +08:00
Promisewjx 9d07b9e227 [Performance] Reduce idle DP work in breakable prefill CUDA graphs (#33871) 2026-08-27 10:09:54 +08:00
Bingxu Chen 4f59a8dcfa [AMD][Bugfix] Skip invalid fused MoE reduction for direct top-1 output (#36309) 2026-08-26 18:52:15 -07:00
Haotong Zou b658d64d5b [CPU] Fix rotary_embedding_cpu fake for in-place layouts (#36443) 2026-08-27 09:48:07 +08:00
Haotong Zou 058f99c561 [CPU] Fix truncated KV prefix in intel_amx spec verify (#36430) 2026-08-27 09:42:36 +08:00
Alison Shao 15688fea7d Fix BailingMoeV3 reading enable_dp_lm_head off live topology instead of config (#36584) 2026-08-26 18:41:39 -07:00
Bingxu Chen 862f9ed3d8 [AMD] Fall back to CPU tensor for decode retraction on ROCm (#36343) 2026-08-26 18:32:51 -07:00
Xinyuan Tongluoyuan.luo得泽翎悦羽癫tiwei.btwLiangsheng Yin文赋JustinTong
 		20621aa14b [Model] Support Ling-3.0-flash (BailingMoeV3) (#33561) 
Signed-off-by: JustinTong <justintong0323@gmail.com>
Signed-off-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
Co-authored-by: 得泽 <zhangkaihong.zkh@antgroup.com>
Co-authored-by: 翎悦 <vito.yy@antgroup.com>
Co-authored-by: 羽癫 <yudian.zy@antgroup.com>
Co-authored-by: tiwei.btw <tiwei.btw@antgroup.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: 文赋 <zibin.zb@antgroup.com>
Co-authored-by: JustinTong <justintong0323@gmail.com>
 2026-08-26 17:27:23 -07:00
paulzhang-tm 8739d56a31 [Spec] Generalize hybrid SWA MTP draft pool routing (#35379) 2026-08-26 17:02:36 -07:00
Liangsheng YincswuygcswuygVedant JhaveriVedant Jhaveri
 		ec4bdbfa4a [Feature] Beam search support (#31626) 
Co-authored-by: cswuyg <cswuyg@gmail.com>
Co-authored-by: cswuyg <496090217@qq.com>
Co-authored-by: Vedant Jhaveri <vedantjh2@gmail.com>
Co-authored-by: Vedant Jhaveri <vjhaveri@linkedin.com>
 2026-08-26 16:56:15 -07:00
Cheng Wan e5a1c5a423 Fix _is_compiling dynamo tracing: import torch instead of sys.modules lookup (#36573) 2026-08-26 16:17:02 -07:00