Ke Bao
|
5609f8e509
|
Reset only the used mamba state on radix cache hit (#31643)
|
2026-07-19 00:40:02 +08:00 |
|
Ke Bao
|
48ae829f6e
|
Reset only the used mamba state on unified radix cache (#31648)
|
2026-07-18 21:43:13 +08:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
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216b750c8f
|
[Kernel] Sweep decoupled scattered kernels into sglang.kernels.ops (RFC #29630) (#31582)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-07-18 19:07:07 +08:00 |
|
 
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9306278fbc
|
vlm: batch cross-request vit encoding and reuse attention metadata (#24013)
Co-authored-by: yhyang201 <yhyang201@gmail.com>
Co-authored-by: Mick <mickjagger19@icloud.com>
|
2026-07-18 18:50:33 +08:00 |
|
Mick
|
573c075fef
|
CI: synchronize prefill graph test fixtures (#31665)
|
2026-07-18 18:48:05 +08:00 |
|
Gabriel Wu
|
faf6894093
|
Implement SM120 DeepSeek V4 flashinfer_mxfp4 moe runner backend + TP2 (#30272)
|
2026-07-18 03:01:06 -07:00 |
|
Mick
|
6c6175fabd
|
perf: avoid excessive prefill CUDA graph padding (#31487)
|
2026-07-18 16:25:30 +08:00 |
|
Baizhou Zhang
|
38b29dcd6c
|
Fix SM120 NVFP4 KV cache test OOM (#31653)
|
2026-07-18 00:53:47 -07:00 |
|
 ThanhhaoandHao Phan
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72c4ed1a3f
|
[Spec] DFlash: remove per-step host syncs so the CPU runs a full step ahead (spec-v2 overlap) (#31468)
Co-authored-by: Hao Phan <htphan@nvidia.com>
|
2026-07-17 23:22:07 -07:00 |
|
Michael
|
7fbe91c6ea
|
[AMD] register 8 JIT kernel benchmarks to jit-kernel-benchmark-test-amd (#31492)
|
2026-07-17 23:00:00 -07:00 |
|
Liangsheng Yin
|
19c53c44a0
|
[Fix] Account zero-logprob sequences correctly in chunked logprob stitching (#31639)
|
2026-07-17 22:33:27 -07:00 |
|
xdtbynd
|
359009fa00
|
[Bugfix][NPU] Fix/Refactor routed scaling factor application in MoE routing (#31449)
|
2026-07-18 10:59:13 +08:00 |
|
Baizhou Zhang
|
304a529558
|
Revert "Bump FlashInfer to 0.6.15 and revert regressions" (#31625)
|
2026-07-17 16:46:33 -07:00 |
|
Lianmin Zheng
|
c95026aed3
|
Upgrade llguidance to 1.7.6 (#31484)
|
2026-07-17 16:31:44 -07:00 |
|
Sam (Kesen Li)
|
ec6a3163b7
|
[Feature] Add FP4 KV Cache Design and support SM120 GPUs (#21601)
|
2026-07-17 14:49:43 -07:00 |
|
Liangsheng Yin
|
2c856abbe3
|
[Fix] Enable chunked input-logprob processing by default to cap peak memory (#31498)
|
2026-07-17 13:19:03 -07:00 |
|
Bingxu Chen
|
53229e88da
|
[AMD] Fix stale imports in test_fused_fp8_kv_write.py (#31515)
|
2026-07-17 09:03:44 -07:00 |
|
Michael
|
c546afc147
|
[AMD] Register 2 CPU/triton unit + kernel tests for AMD 1-GPU PR CI (#31379)
|
2026-07-17 09:01:46 -07:00 |
|
 NOOBandR0CKSTAR
|
5e7eed4c00
|
[MLX] Honor --max-running-requests in the model runner stub (#30547)
Co-authored-by: R0CKSTAR <yeahdongcn@gmail.com>
|
2026-07-17 08:24:00 -07:00 |
|
Mick
|
681c223570
|
refactor: wrap split backends once on full-attention backends (#31439)
|
2026-07-17 19:15:04 +08:00 |
|
Mick
|
24a8944e15
|
fix: enable Kimi multimodal breakable prefill cuda graph replay (#31391)
|
2026-07-17 19:13:54 +08:00 |
|
 
|
132ade55cd
|
[Kernel] Rewrite JIT custom all-reduce (v2) with a decoupled kernel/storage design (#31049)
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Co-authored-by: root <root@GPUC5A6.maas>
|
2026-07-17 18:37:22 +08:00 |
|
 Mohammad Miadh AngkadandBrayden Zhong
|
d67aa05697
|
Bump FlashInfer to 0.6.15 and revert regressions (#31502)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
|
2026-07-17 00:50:12 -07:00 |
|
Baizhou Zhang
|
e835512303
|
Add nightly test for GLM5.2 LayerSplit (#31512)
|
2026-07-17 00:29:14 -07:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
|
619609aa5a
|
[Kernel] Simplify sglang.kernels tests to idiomatic pytest style (RFC #29630) (#31546)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-07-17 15:06:26 +08:00 |
|
 huangtingweiandZhangheng
|
44e3dd2713
|
[HiCache] Optimize HiCache host pool free-list release (#30658)
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-07-17 14:52:08 +08:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
|
1ac1ffea0c
|
[Kernel] Fill non-CUDA coverage: HIP (aiter/rocm-triton) + Ascend NPU backends (RFC #29630) (#31307)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-07-17 14:05:35 +08:00 |
|
NOOB
|
444bbd866d
|
[CI] Fix invalid suite name breaking all PR test lanes (#31539)
|
2026-07-16 22:30:05 -07:00 |
|
 AuFlowandAuFlow
|
bf417440e9
|
[Scheduler] Add SGLANG_MAX_NEW_TOKENS_LIMIT to cap per-request max_new_tokens (#22591)
Co-authored-by: AuFlow <AuFlow@users.noreply.github.com>
|
2026-07-16 21:34:10 -07:00 |
|
Ma Mingfei
|
486a56be56
|
[CPU] improve silu performance by replacing fp32 div with rcp14 (#31304)
|
2026-07-17 12:02:37 +08:00 |
|
 Xiaoyu ZhangandClaude Opus 4.8
|
8432eafd3d
|
[Kernel] Decouple KernelBackend from device + device-based CapabilityRequirement (RFC #29630) (#31292)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-07-17 10:35:34 +08:00 |
|
 Polisetty V R K Jyothendra VarmaandRahul Vijayaraghavan
|
37f94cb7a0
|
[Intel GPU] DeepSeek V4 13/N: use sgl-kernel implementation of kernels in V2 Compressor to run on XPU (#28439)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
|
2026-07-17 09:16:04 +08:00 |
|
Kaixi
|
dc0b3eb68f
|
[2/3] [EAGLE] perf: Fuse TP vocab-parallel embedding (#30948)
|
2026-07-16 15:57:51 -07:00 |
|
Kaixi
|
d539bf2cda
|
[1/3] [EAGLE] perf: Fuse topk=1 draft postprocess (#30947)
|
2026-07-16 15:57:27 -07:00 |
|
Yoray Zack
|
77d23a796e
|
[1/N] elastic-ep: Add runtime EP scale-up (#30164)
|
2026-07-16 15:53:44 -07:00 |
|
Liangsheng Yin
|
640101da13
|
[Fix] Deflake score engine determinism tests (#31494)
|
2026-07-16 15:42:47 -07:00 |
|
 Bob ChenandZhiqiang Xie
|
7cd55c6818
|
[HiCache] Optimize L2 mem allocation when cache miss in L3 (#19320)
Co-authored-by: Zhiqiang Xie <xiezhq@stanford.edu>
|
2026-07-16 15:00:53 -07:00 |
|
Liangsheng Yin
|
fc1e3797b7
|
[Spec] Split the capture width from num_tokens_per_req and gate replay on it (#31255)
|
2026-07-16 14:59:11 -07:00 |
|
Serge Panev
|
1f34911de7
|
[NemotronH] Load shared embed_tokens/lm_head in MTP draft weights (#30456)
|
2026-07-16 17:20:38 +00:00 |
|
pllimax
|
4ad418d2c3
|
Push test case scripts from test repo to main upstream community repository (#31114)
|
2026-07-16 21:24:01 +08:00 |
|
Mick
|
7d0fd5101d
|
optimization: shard kimi dp image feature transport and misc optimizations (#31227)
|
2026-07-16 20:31:42 +08:00 |
|
 jojoandhzh0425
|
b296e1a503
|
[hicache]: add mamba concurrency io transfer kernel (#30535)
Co-authored-by: hzh0425 <hzh0425@apache.org>
|
2026-07-16 18:13:02 +08:00 |
|
Wang, FangYuan
|
e2d021d4ab
|
[AMD] Support two batch overlap with MTP on DeepSeekV4 (#30238)
|
2026-07-16 02:34:04 -07:00 |
|
 
|
e5f9804e26
|
Refining fused A GEMM dispatch (#31241)
Co-authored-by: root <root@sgl-b300-inference.datacrunch.io>
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
|
2026-07-16 16:57:01 +08:00 |
|
 Yuan Luoandluoyuan.luo
|
a798a2aeea
|
[GDN/KDA] Fuse SM100 CuteDSL prefill state I/O into the chunk h kernel (#30169)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
|
2026-07-16 16:40:33 +08:00 |
|
 
|
db7e6807de
|
[BugFix] Preserve tokenizer worker fanout when skip_tokenizer_init is enabled (#30682)
Co-authored-by: hjzhang <zhanghjzzz@qq.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
|
2026-07-16 01:29:46 -07:00 |
|
zhengyao
|
01b003255a
|
[AMD]Reuse fused FP8 KV cache write on standard aiter prefill/decode (#26852)
|
2026-07-16 01:05:04 -07:00 |
|
  
|
095a817612
|
[Bugfix][HiCache] measure load-back duration with CUDA events (#26411)
Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
Co-authored-by: vuuihc <vuuihc@users.noreply.github.com>
Co-authored-by: Zhiqiang Xie <xiezhq@stanford.edu>
|
2026-07-16 00:11:04 -07:00 |
|
Xiaoyu Zhang
|
e73f323464
|
[JIT] Reduce MoE fused gate CI test sweep (#31400)
|
2026-07-16 14:42:45 +08:00 |
|
 Ryan Zzzandzhujunyu
|
5af65d8542
|
[DeepSeek-V4] Support BF16 Compress State for Online C128 (#29609)
Co-authored-by: zhujunyu <zhujunyu.666@bytedance.com>
|
2026-07-15 23:17:29 -07:00 |
|