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Author SHA1 Message Date
Mohammad Miadh AngkadandMohammad Angkad 52c191da52 [Deps] Retire the CUDA 12 lane (#38404) 
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
 2026-09-10 16:58:09 -07:00
rystewart-nvidiaelvischenvPo-Han Huang
 		fae8cd84cb Support NemotronH_Omni_Reasoning_V3 in SGLang (#35599) 
Signed-off-by: Ryan Stewart <rystewart@nvidia.com>
Signed-off-by: rystewart-nvidia <rystewart@nvidia.com>
Co-authored-by: elvischenv <219235043+elvischenv@users.noreply.github.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
 2026-09-10 16:57:22 -07:00
cctry 203d7e812c Fix KV-canary workspace accounting after graph capture (#38596) 2026-09-10 16:10:12 -07:00
cctry 42bbaac259 [metrics] Report logical prefill token counts (#38566) 2026-09-10 16:09:21 -07:00
Liangsheng Yin dc5f59c3a2 [Refactor] Clarify DeepSeek V4 metadata names for V4.1 (#38947) 2026-09-10 15:42:52 -07:00
Pengyun Lin d076eec427 [SM120] Use exact query-head widths for DeepSeek-V4 sparse MLA decode (#36655) 2026-09-10 15:40:17 -07:00
paulzhang-tmandQiaolin-Yu bb15be6d79 [Spec] Stage Inkling MTP draft metadata before verify (#38169) 
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
 2026-09-10 15:32:19 -07:00
paulzhang-tm a63efd9056 [Spec] Support large MTP batches in short-convolution metadata (#38558) 2026-09-10 15:13:17 -07:00
Byron HsuByronHsurootByron Hsu
 		fd7743e0e1 [Sampling] Support sampling masks with overlap scheduling (#36631) 
Co-authored-by: ByronHsu <ByronHsu@users.noreply.github.com>
Co-authored-by: root <root@slurm-h200-208-179.slurm-compute.tenant-slurm.svc.cluster.local>
Co-authored-by: Byron Hsu <byron+per@periodiclabs.ai>
 2026-09-10 14:52:44 -07:00
YAMY 55b45cb45a fix(qsa): dequantize FP8 cached prefixes in the sparse prefill kernels (#38855) 2026-09-10 14:07:39 -07:00
Kangyan-ZhouKangyan ZhouClaude Opus 5
 		06dfe05d65 [Deps] Raise smg-grpc-servicer floor to >=0.9.0 to unbreak SMG E2E CI (#38801) 
Co-authored-by: Kangyan Zhou <kangyan.zhou@radixark.ai>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
 2026-09-10 13:55:36 -07:00
zijiecZijie Chenjacky.cheng
 		a26273d668 [AMD] Quantize the bf16 MTP draft experts online to MXFP4 for Qwen3.5 (#38748) 
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
 2026-09-10 13:00:41 -07:00
sglang-botandsglang-bot 887c401e15 docs: sync LMSYS SGLang blog cards (#36773) 
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
 2026-09-10 18:37:14 +00:00
zijiexiaandClaude Opus 5 4b7331fb77 Make the remaining DeepSeek-V4.1 NVIDIA cells start (#38861) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-09-10 11:04:53 -07:00
James 209654c420 [NPU][Hicache] Optimize HiCache L2 IO with Memfabric acc_offload (#38826) 2026-09-11 00:23:36 +08:00
Shuwen Wang 19b83b4b9d [Radix Cache] Fix PureSWA tail release without insertion (#38349) 2026-09-10 23:55:48 +08:00
Shuwen Wang cc7e43ad22 [HiCache] Account for newly pinned ancestors in load-back quota (#38481) 2026-09-10 23:54:08 +08:00
pllimax 92dffebe16 [NPU] Set DEEPEP_HYBRID_DEPLOYMENT for new DeepEP tests; switch glm5_2 to w8a8; tune nightly timeouts (#38775) 2026-09-10 23:32:54 +08:00
Chengze Fan 12771786f2 [AMD] Restore AITER verify runtime sizing reverted by #34647 (#38575) 2026-09-10 05:57:47 -07:00
Mohammad Miadh AngkadandMohammad Angkad 613002281e [CI] Drop the GPTQ dynamic-config test for the deleted non-Marlin kernel (#38881) 
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
 2026-09-10 20:55:06 +08:00
Jialin Ouyang 908226fea2 [Rust TreeCore] Support external cache linker (#37306) 2026-09-10 19:22:24 +08:00
liupeng374 334e94d8ac [NPU] fix pp 2 hang on npu (#38249) 2026-09-10 19:21:37 +08:00
Yuhao YangandClaude Code a37ded1693 [Cookbook] DeepSeek-V4.1: add the HiCache L2 knob to the Playground (#38844) 
Co-authored-by: Claude Code <noreply@anthropic.com>
 2026-09-10 18:20:34 +08:00
Mohammad Miadh AngkadandMohammad Angkad dc2157dcd6 [JIT] Port the expert-pack MXFP4 kernels to load_jit and fix their launch limits (#38830) 
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
 2026-09-10 17:50:51 +08:00
Mohammad Miadh Angkad 8022505705 Revert "[CI] Temporarily disable GB300 tests" (#38842) 2026-09-10 02:41:15 -07:00
MickandMick Qian c9c26d56b2 [diffusion] docs: sync snapshot and minimax-h3 subblock features (#38784) 
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
 2026-09-10 17:23:43 +08:00
Clintclintg6HAI
 		8a6ab89bf0 [AMD] Enable Fast Triton Sparse MLA backend (#30575) 
Co-authored-by: clintg6 <7388379+clintg6@users.noreply.github.com>
Co-authored-by: HAI <hixiao@gmail.com>
 2026-09-10 01:58:00 -07:00
zijiexiaandClaude Opus 5 5caafd2118 Fix the DeepSeek-V4.1 reasoning example and mark the B300 cells verified (#38839) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-09-10 01:49:44 -07:00
Baizhou Zhang fa6e657b93 [misc] Update CI permission (#38834) 2026-09-10 01:38:58 -07:00
ashwini rathi b23db06769 pyproject(xpu): drop human-eval git dep to unblock image build (#38824) 2026-09-10 16:24:43 +08:00
Adarsh ShirawalmathXinyuan TongAlex Nails
 		55b4f4f195 [Test] Add offline Transformers loader compatibility checks (#38336) 
Signed-off-by: adarshxs <adarsh.shirawalmath@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
 2026-09-10 01:07:43 -07:00
Xinyuan Tong 9a2f17f41d Add INT4 and FP4 lanes to the Ling-3.0-flash-VL cookbook (#38527) 2026-09-10 15:23:50 +08:00
Shu Wangdjns99云挚Yangmin LiPo-Han Huang
 		1b77f498a0 [NVIDIA] Support flashinfer Mega Moe (#31470) 
Co-authored-by: djns99 <40156487+djns99@users.noreply.github.com>
Co-authored-by: 云挚 <ningyunxiao.nyx@antgroup.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
 2026-09-10 00:22:47 -07:00
Brayden ZhongandBrayden Zhong c0b790cf7f Delete cutlass_mla, non-Marlin GPTQ, AWQ AOT kernel, and Dual Chunk Flash Attention (#32114) 
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
 2026-09-10 15:12:01 +08:00
Brayden ZhongandBrayden Zhong 7152c14384 Fix DeepSeek-V4 routing: sqrtsoftplus underflow and unfloored renorm (#34459) 
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
 2026-09-10 15:10:50 +08:00
YC Yen-Ching Tseng 6b2e13bcb0 [AMD] Fix the diffusion perf fixture lookup (#38686) 2026-09-10 00:07:08 -07:00
Bingxu Chen bd922bc39b [AMD][CI] Fix UMBP test buffer after MoRI upgrade (#38672) 2026-09-10 00:02:00 -07:00
MichaelCursor AgentMichael
 		13fb796c81 [AMD][CI] Drop the dead miles ROCm 7.0 nightly image build (#38694) 
Co-authored-by: Cursor Agent <cursoragent@cursor.com>
Co-authored-by: Michael <michaelzhang-ai@users.noreply.github.com>
 2026-09-10 00:00:28 -07:00
Michael 026e61bd94 [AMD] Restore AMD CI registrations dropped by #37436 (#38581) 2026-09-09 23:59:10 -07:00
Michael f3152439d0 [AMD][CI] Publish ROCm 10 release images and kernel wheel (#38763) 2026-09-09 23:57:00 -07:00
ashwini rathi a1ec35a330 docker(xpu): install libssl-dev so JIT hicache_hash_cpp builds (#38796) 2026-09-10 14:37:20 +08:00
Shuwen Wang 058cca0192 [HiCache] Fix side pools to use resolved host allocator (#38350) 2026-09-10 14:28:20 +08:00
zijiexiaandClaude Opus 5 69777c4d36 Add DeepSeek-V4.1 Flash cookbook (#38802) 
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
 2026-09-09 23:15:30 -07:00
DAI0818andPo-Han Huang 03e4c06589 Fix Qwen3.5 GDN multi-item scoring (#33922) 
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
 2026-09-09 22:30:39 -07:00
Kan WuandClaude Fable 5 6f481ad0e3 [router] Raise chat body cap to 32 MB for multimodal payloads (#38735) 
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
 2026-09-09 22:14:49 -07:00
Sage 01ad27ecd9 [CPU] Fix native KV hash compilation in Xeon image (#34767) 
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
 2026-09-10 12:51:25 +08:00
ashwini rathiandarathi-hlab 6ab6df54b9 Add missing test dependencies to pyproject.toml variants (#36098) 
Co-authored-by: arathi-hlab <arathi.rajendran@intel.com>
 2026-09-10 12:49:16 +08:00
Thomas Wang c415f977b8 [AMD] Update v4 args for agentic workload (#38677) 2026-09-09 21:41:05 -07:00
Alison Shao 2f7393f0d2 [Simulator] Give the OFFLINE/BLOCKING comparison tolerances real headroom (#38732) 2026-09-10 11:10:38 +08:00
Cheng Wan f1a512c51c [Config] msgspec.Struct for the config tier (#38753) 2026-09-09 19:41:19 -07:00