Commit Graph
10009 Commits
Author SHA1 Message Date
Mick 42acfd1550 [diffusion] feat: performance_mode=speed enables torch.compile by default (#30016) 2026-07-03 19:12:17 +08:00
khalilzhk 430418e218 [NPU] bugfix for dsv4 memory pool (#30001) 2026-07-03 16:41:39 +08:00
Baizhou Zhang e3258d3b54 [Fix] Turn off dsa indexer fusion by default (#30018) 2026-07-03 01:08:06 -07:00
Polisetty V R K Jyothendra VarmaandMa Mingfei 4dddb04325 [Intel GPU] DeepSeek V4 6/N: use sgl-kernel implemetation of flash_mla_with_kvcache on XPU (#27914)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-03 15:59:38 +08:00
e90fec4868 [Intel GPU] DeepSeek V4 10/N : Add sqrtsoftplus support to fused_topk_torch_native (#28048)
Signed-off-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-03 15:59:12 +08:00
Cao E 9df16b5ba9 [XPU] Remove redundant xpu graph backend and make xpu graph opt-in by default (#29911) 2026-07-03 15:58:56 +08:00
McZyWu 8416544ab0 [NPU] bugfix for Base class add mamba_track_indices parameter (#29999) 2026-07-03 15:10:41 +08:00
Chandrakant Khandelwal fe60764f54 [diffusion] fix: add profiling support and fix VBench dataset handling in bench_offline_throughput (#27704) 2026-07-03 15:08:38 +08:00
Cheng Wan 76f7f7c006 [Spec] Remove the ServerArgs clone + global save/restore hack from DFlashWorkerV2 (#29995) 2026-07-02 23:37:04 -07:00
xutizhou d364cd8ead Support DSV4 shared expert fusion for DeepEP and MegaMOE (#27349) 2026-07-02 23:18:25 -07:00
YAMY e81f05cf4f [dsv4] Trigger MHC prenorm prewarm at weight-load time with rank sync (#29988) 2026-07-02 23:05:03 -07:00
YAMY a6ee64d237 [DeepSeek-V4] Add an opt-in non-paged indexer for long-context prefill (#29619) 2026-07-02 22:54:40 -07:00
san-tianandSan Tian 70b6c06793 fix: avoid DSA indexer CPU seq lens fallback (#29798)
Co-authored-by: San Tian <san-tian@users.noreply.github.com>
2026-07-02 22:50:24 -07:00
Yiqi YangandMick e878c6ebdd [diffusion] feat: shard qwen-image dit across tp ranks (#29774)
Co-authored-by: Mick <mickjagger19@icloud.com>
2026-07-03 13:17:53 +08:00
Yiqi Yang f011d8c2e5 [Anthropic] Fix missing cache_read_input_tokens in streaming responses (#29703) 2026-07-03 12:46:45 +08:00
Ke Bao 372a893744 Move deferred mamba cow and clear (#29945) 2026-07-03 11:29:05 +08:00
Xiaoyu ZhangandClaude Opus 4.8 a2d7eb303e [MoE] Consolidate ungrouped + grouped gate/topk onto one Triton router (#26771) — faster than AOT on B200/H100/H200, at parity with flashinfer (#29771)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
2026-07-03 11:18:59 +08:00
Michael bee0f34e68 [AMD] Accept ROCm tensors in JIT kernel TensorMatcher + register 4 kernel tests (#29822) 2026-07-02 19:29:47 -07:00
YC Yen-Ching Tseng 05bc3f2aa7 [AMD] Gate broken CK block-FP8 GEMM shapes to aiter-triton-GEMM to fix ROCm 7.0 Qwen3.5 accuracy (#29918) 2026-07-02 18:18:37 -07:00
Po-Han Huang (NVIDIA) 17cce6a85f Fix shared logits buffer for reduced-vocab draft models (#29943) 2026-07-02 16:08:56 -07:00
Michael 8519be82e8 [AMD][DeepSeek V4] Fix default FlashMLA sparse prefill off on ROCm/HIP (#29982) 2026-07-02 16:00:09 -07:00
Oxana Korzh f3904f0293 [bugfix][AMD] Disable aiter allreduce+RMSNorm fusion under DP attention / EP (#27835) 2026-07-02 15:31:25 -07:00
YukioZzzandDuyi-Wang caf2e5da2d [AMD] Fix MiniMax M3 state transfer in Mori PD (#29756)
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
2026-07-02 15:02:10 -07:00
Rain Jiang ae1f0c6d07 session_id dataclass field should not put in msgpack struct (#29977) 2026-07-02 14:10:12 -07:00
Mohammad Miadh Angkad cfb9c574d3 Fix UE8M0 scale rounding for DeepGEMM (#29956) 2026-07-02 13:42:17 -07:00
Cheng Wanandlch1475369 bc25abb786 perf(triton): avoid per-step D2H .item() sync in cuda-graph loc translate (#29921)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
2026-07-02 13:20:00 -07:00
Zhiqiang Xie f19246e59a [HiCache] write_back policy refinement (#29817) 2026-07-02 12:16:03 -07:00
Brayden ZhongandBrayden Zhong 1b6d1e9752 Fix wrong RMSNorm fallback to old Flashinfer CUDA kernel when in PCG (#29702)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
2026-07-03 00:49:49 +08:00
Xinyuan Tong 9588cacaa1 Remove transformers 5.12.1 dead-code workarounds (#29758) 2026-07-03 00:03:06 +08:00
McZyWu c05c48b35e bugfix for npu Grok2 model --detokenizer without all special ids (#29853) 2026-07-02 22:12:48 +08:00
McZyWu bdd3515389 NPU case rl update weights for tensor load_format == None and flatten bucket (#29503) 2026-07-02 22:12:05 +08:00
Ke Bao a375e9f3da Fix SWA eviction tombstoning the last leaf (#29860) 2026-07-02 21:42:30 +08:00
Mick 3c1adddff9 [diffusion] refactor: refactor cuda attention backend resolver (#29852) 2026-07-02 21:34:54 +08:00
Mick 119b76567d [diffusion] feat: add --offload-during-compile to fit max-autotune on tight-memory GPUs (#29862) 2026-07-02 19:39:19 +08:00
26b15a0825 [LFM2-MoE] Support Transformers v5 packed MoE expert weights (#29659)
Co-authored-by: Piotr Mazurek <piotr.mazurek@liquid.ai>
Co-authored-by: Changyi Yang <changyiyang2023@gmail.com>
2026-07-02 17:13:02 +08:00
Xiaoyu Zhang b276a9acee chore: cleanup garbage code (#29770) 2026-07-02 16:14:01 +08:00
cctry 697b400d70 Share one logits output buffer across prefill/decode/draft cuda-graph runners (#29779) 2026-07-01 23:30:56 -07:00
Cao E 926140d789 [XPU] Enable XPU graph support (decode full-graph + prefill tc_piecewise) (#29053) 2026-07-02 13:24:35 +08:00
ANSHUMAN TRIPATHY 4fffc6448b Speculative decoding support on XPU (#23180) 2026-07-02 13:23:24 +08:00
790156c98f [Intel GPU] DeepSeek V4 7/N: Support fused_rope_inplace on XPU using triton (#27915)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-02 13:22:20 +08:00
Zaili Wang cb06c4e6ce [CPU] Fix model failures on Xeon (#29497) 2026-07-02 13:20:18 +08:00
Zaili WangandMa Mingfei aff44d748d [CPU] Padding for dim divisibility in TP3/6 cases (#20072)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-07-02 13:14:39 +08:00
cctry 80ac11eda3 Fix capture-mode detection during breakable CUDA graph capture (#29866) 2026-07-01 22:12:56 -07:00
sushil Dubey e88645d65f [amd][diffusion] fix: fix causal Conv3D cat/pad fusion crashes for wan2.2 t2v (#29672)
Signed-off-by: Sushil Dubey <sushilghansyam.dubey@amd.com>
2026-07-02 13:11:30 +08:00
Yuwei An 0543246184 Enable Breakable Cuda Graph as Default (#29458) 2026-07-01 22:04:44 -07:00
d15b79e96e [bug6] clear stale mamba cow source on rematch (#29354)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Hanming Lu <hanminglu@meta.com>
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
2026-07-02 13:04:09 +08:00
YAMYandYuwei An 307094dc7d [DeepSeek V4] Cover both dense and sparse prefill paths in the compress attention unittest (#29885)
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
2026-07-01 21:20:12 -07:00
Feng Yao e6f6a353bf pad customized_info for mixed output batches (#29842) 2026-07-02 12:07:58 +08:00
Yuan Luoandluoyuan.luo eb23f9a86b [KDA] Add FlashKDA prefill backend for safe-gate KDA linear attention (#29472)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
2026-07-02 11:37:04 +08:00
6eeb9871e5 Add Laguna XS.2.1 DFlash support to SGLang (#29446)
Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
2026-07-01 20:26:23 -07:00