[AMD] Accept ROCm tensors in JIT kernel TensorMatcher + register 4 kernel tests (#29822)
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@@ -62,11 +62,11 @@ void add_constant(tvm::ffi::TensorView dst, tvm::ffi::TensorView src) {
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// 1. Validate input tensors
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SymbolicSize N = {"num_elements"};
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SymbolicDevice device_;
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TensorMatcher({N}) // 1D tensor, must be contiguous
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.with_dtype<int32_t>() // must be int32
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.with_device<kDLCUDA>(device_) // must be on CUDA device
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.verify(dst) // check tensor dst
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.verify(src); // check tensor src
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TensorMatcher({N}) // 1D tensor, must be contiguous
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.with_dtype<int32_t>() // must be int32
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.with_device<kDLGPU>(device_) // must be on GPU device (CUDA or ROCm)
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.verify(dst) // check tensor dst
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.verify(src); // check tensor src
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// 2. Extract required parameters, prepare for kernel launch
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const size_t num_elements = N.unwrap();
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@@ -177,19 +177,19 @@ struct CausalConv3dCatPadKernel {
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auto out_h = SymbolicSize{"out_h"};
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auto out_w = SymbolicSize{"out_w"};
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auto device = SymbolicDevice{};
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device.set_options<kDLCUDA>();
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device.set_options<kDLGPU>();
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TensorMatcher({bsz, channels, t_size, h_size, w_size})
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.with_dtype<T>()
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.template with_device<kDLCUDA>(device)
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.template with_device<kDLGPU>(device)
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.verify(x);
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TensorMatcher({bsz, channels, cache_t, h_size, w_size})
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.with_dtype<T>()
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.template with_device<kDLCUDA>(device)
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.template with_device<kDLGPU>(device)
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.verify(cache);
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TensorMatcher({bsz, channels, out_t, out_h, out_w})
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.with_dtype<T>()
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.template with_device<kDLCUDA>(device)
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.template with_device<kDLGPU>(device)
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.verify(out);
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const int64_t depth_left = pad_d_left - cache_t.unwrap();
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@@ -209,47 +209,47 @@ struct NgramEmbeddingKernel {
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// Verify tensor shapes and types using -1 (kAnySize) for dynamic dimensions
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TensorMatcher({-1, -1, -1}) // [ne_n-1, ne_k, ne_n]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>(device_)
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.with_device<kDLGPU>(device_)
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.verify(ne_weights);
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TensorMatcher({-1, -1}) // [ne_n-1, ne_k]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ne_mods);
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TensorMatcher({-1}) // [(ne_n-1)*ne_k + 1]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(exclusive_ne_embeder_size_sums);
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TensorMatcher({-1}) // [token_num]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(tokens);
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TensorMatcher({-1}) // [batch_size+1]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(exclusive_req_len_sums);
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TensorMatcher({-1, -1}) // [max_running_reqs, max_context_len]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ne_token_table);
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TensorMatcher({-1}) // [batch_size]
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.with_dtype<int64_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(row_indices);
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TensorMatcher({-1}) // [batch_size]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(column_starts);
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TensorMatcher({-1, -1}) // [token_num, (ne_n-1)*ne_k]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(n_gram_ids);
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const int batch_size = static_cast<int>(exclusive_req_len_sums.size(0) - 1);
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@@ -294,37 +294,37 @@ struct NgramEmbeddingKernel {
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TensorMatcher({-1, -1, -1}) // [ne_n-1, ne_k, ne_n]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>(device_)
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.with_device<kDLGPU>(device_)
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.verify(ne_weights);
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TensorMatcher({-1, -1}) // [ne_n-1, ne_k]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ne_mods);
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TensorMatcher({-1}) // [(ne_n-1)*ne_k + 1]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(exclusive_ne_embeder_size_sums);
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TensorMatcher({-1, -1}) // [max_running_reqs, max_context_len]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ne_token_table);
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TensorMatcher({batch_size}) // [batch_size]
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.with_dtype<int64_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(row_indices);
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TensorMatcher({batch_size}) // [batch_size]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(column_starts);
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TensorMatcher({batch_size, -1}) // [batch_size, (ne_n-1)*ne_k]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(n_gram_ids);
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const int bs = static_cast<int>(batch_size.unwrap());
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@@ -371,27 +371,27 @@ struct NgramEmbeddingKernel {
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// Verify tensor shapes and types using -1 (kAnySize) for dynamic dimensions
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TensorMatcher({-1}) // [token_num]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>(device_)
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.with_device<kDLGPU>(device_)
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.verify(tokens);
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TensorMatcher({-1, -1}) // [max_running_reqs, max_context_len]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ne_token_table);
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TensorMatcher({-1}) // [batch_size]
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.with_dtype<int64_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(row_indices);
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TensorMatcher({-1}) // [batch_size]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(column_starts);
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TensorMatcher({-1}) // [batch_size]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(req_lens);
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// ignore_tokens can be empty or have values
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@@ -400,7 +400,7 @@ struct NgramEmbeddingKernel {
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if (has_ignore_tokens) {
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TensorMatcher({-1}) // [ignore_token_num]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ignore_tokens);
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}
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@@ -447,22 +447,22 @@ struct NgramEmbeddingKernel {
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TensorMatcher({batch_size}) // [batch_size]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>(device_)
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.with_device<kDLGPU>(device_)
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.verify(tokens);
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TensorMatcher({-1, -1}) // [max_running_reqs, max_context_len]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(ne_token_table);
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TensorMatcher({batch_size}) // [batch_size]
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.with_dtype<int64_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(row_indices);
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TensorMatcher({batch_size}) // [batch_size]
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.with_dtype<int32_t>()
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.with_device<kDLCUDA>()
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.with_device<kDLGPU>()
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.verify(column_starts);
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const int bs = static_cast<int>(batch_size.unwrap());
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