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42875bcd2a
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fix(modelopt): dispatch NVFP4 MoE on the cached backend, not the live global (#38932)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-20 19:28:54 -04:00 |
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Mohammad Miadh Angkadandmmangkad
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2fa6b94e34
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[Perf] Fuse the glm5_next mHC attn->MLP boundary (#39200)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
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2026-09-20 16:20:37 -07:00 |
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ollybbmonster
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983e643854
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[Feature] support bf16 MoE router and mxfp4 MoE for MiMo V2 (#40448)
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2026-09-20 16:13:59 -07:00 |
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luoroger37andHank Han
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d97aed2c90
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Fix TopK v2 fallback when 16-block cluster capacity is zero (#40163)
Co-authored-by: Hank Han <hanhan7630@outlook.com>
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2026-09-21 06:41:41 +08:00 |
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f31a7bd45c
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Use pinned memory for asynchronous sampling metadata transfers (#39777)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-09-20 15:31:31 -07:00 |
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Harmya Bhatt
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95521da18d
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[DeepSeek-V4.1] Bound dense prefill indexer memory (#40217)
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2026-09-20 14:43:19 -07:00 |
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c2c3629f2d
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[Kimi-K3] O(1) expert weight lookup in load_weights (#38805)
Signed-off-by: JinYan Su <751080330@qq.com>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-09-20 14:39:45 -07:00 |
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d229952e25
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[Fix] Preserve model runner contracts in prefill CUDA graphs (#35452)
Co-authored-by: Oasis-Git <ayw.sirius19@gmail.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-20 13:53:14 -07:00 |
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Khoa Pham
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b3e4d198af
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[PD] Bound cached-prefix DCP transfers by pack capacity (#40376)
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2026-09-21 01:17:15 +08:00 |
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Jimmy ShongandYangmin Li
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e97614d10c
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[Qwen4-Exp] Build the offloaded PLE table on the meta device so --ple-offload-embedding never materialises it on the accelerator (#39928)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
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2026-09-20 08:28:25 -07:00 |
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ZY Y
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5f017ffabb
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Update test cases and performance testing framework (#40392)
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2026-09-20 22:42:00 +08:00 |
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faceless voidandronnie_zheng
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791c7850d0
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[Diffusion] Enable shared RMSNorm dispatch for SenseNova-U1 (#39705)
Signed-off-by: syd520zy <529477025@qq.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
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2026-09-20 17:08:02 +03:00 |
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HuangJi
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2a0cb2f04e
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[Diffusion][MiniMax-H3] Add SM120 Sage compute for SubBlock sparse attention (#40116)
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2026-09-20 16:40:28 +08:00 |
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Shuwen WangandSeokhoon Kang
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9f3d275940
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[HiCache] Fix sparse hybrid transfer layer IDs (#37870)
Co-authored-by: Seokhoon Kang <sh.kang@postech.ac.kr>
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2026-09-20 16:24:24 +08:00 |
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amd-danli103andHAI
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e54009240a
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[AMD][DSV4] feat: enable DSpark with fp8 unified_kv on gfx950 (#38901)
Co-authored-by: HAI <hixiao@gmail.com>
|
2026-09-20 01:16:39 -07:00 |
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Ke Bao
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a8a4d86be9
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Remove swa and mamba radix cache (#40313)
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2026-09-20 16:16:27 +08:00 |
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Qiaolin Yu
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f4c256354c
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[kimi k3][pd disagg] support pp prefill + dcp decode with dspark (#40045)
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2026-09-20 00:15:28 -07:00 |
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99a44c88d4
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Add out-of-tree DFlash extension points (#38740)
Co-authored-by: Yuhan Chen <yuhanc@fb.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-20 14:54:46 +08:00 |
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Yuxuan ZhangandXinyuan Tong
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9f21fbc34b
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[GLM-5.3-Flash] Reduce KPool planning synchronization and overlap indexer preparation (#39695)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-19 23:51:17 -07:00 |
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Yuxuan ZhangandXinyuan Tong
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c8eb54c41d
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Fuse GLM-5.3-Flash KDA projections and prefill metadata (#39688)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-19 23:46:33 -07:00 |
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chaijiacheng888
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2d216a11f8
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[Model] Serve DeepSeek-OCR-2 with its official 768px local-crop geometry (#38996)
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2026-09-20 14:17:21 +08:00 |
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MickandMick Qian
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031bff5dd3
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[diffusion] chore: batch qwen-image 2.1 targets and document measured deployment recipes (#40408)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-20 13:59:36 +08:00 |
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Sasha Sidorov
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59dd2fc734
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[2/N] [Kernel] Fuse padding-preserving HiSparse slot translation (#39837)
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2026-09-20 12:04:03 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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df0dc44931
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[Fix] Forward SWA prealloc reclaim through the DSV4 HiSparse allocator (#40354)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-19 20:27:51 -07:00 |
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huangtingweiandChao Shi
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020703923d
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[PP + HiCache] Add PP Prefetch Tickets for eager cross-stage storage prefetch (#36700)
Co-authored-by: Chao Shi <stepinto@live.com>
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2026-09-20 11:19:31 +08:00 |
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113f6f080e
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[PD] Enter the custom mem pool once when allocating DCP pack buffers (#40284)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
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2026-09-19 19:34:58 -07:00 |
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Tri Dao
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d82d653f96
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Enable optimistic prefill for Mamba radix-cache models (#40184)
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2026-09-19 19:28:11 -07:00 |
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huangtingweiandZhangheng
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e9300f643e
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[Unified Cache][9/N] add opt-in MLA load deduplication for Mooncake Linker (#39565)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-20 09:56:56 +08:00 |
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AndyLi429andAndyLi429
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d903351a66
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[NPU][bugfix] update low latency quantization input and update MXFP8 tests (#38831)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
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2026-09-20 09:55:30 +08:00 |
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f9c2791460
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[diffusion] model: support qwen-image-2.1 (#39983)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
Co-authored-by: BBuf <1182563586@qq.com>
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2026-09-20 09:46:09 +08:00 |
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BourneSun0527andEven Zhou
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d2f291c934
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[NPU][DSV4]dsv4 enable cpp (#39820)
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
|
2026-09-20 09:17:27 +08:00 |
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YAMY
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9cc7da2ab0
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[MegaMoE] Wire Qwen MoE blocks to DeepGEMM MegaMoE (MXFP4 and NVFP4 experts) (#38080)
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2026-09-19 16:00:38 -07:00 |
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3a64faa1f2
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Fix disagg PP MTP for GLM-5.2 (#39378)
Co-authored-by: Julien Lin <jullin@nvidia.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
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2026-09-19 13:55:07 -07:00 |
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8139a1740e
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[Scheduler] Count complete prefill bursts and their tokens (#40006)
Co-authored-by: pranjalssh <pranjalssh@fb.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
Co-authored-by: Jialin Ouyang <jialino@meta.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
|
2026-09-19 12:56:15 -07:00 |
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Zhiqiang Xie
|
7a6c652c77
|
[HiCache] Auto-size the host pool to fit available host memory (#40135)
|
2026-09-19 12:50:43 -07:00 |
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amd-danli103
|
2305242f51
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[AMD][DSV4] fix: skip compressed-KV metadata on the draft worker in the HIP radix backend (#40205)
|
2026-09-19 12:13:49 -07:00 |
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metamergebotandcctry
|
9e5a62a767
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[Logprob] Serve input-logprob temporaries from CUDA-graph-pool dead space (#40038)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-19 12:03:52 -07:00 |
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kkandwunhuang
|
c5326d28a3
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[AMD] dsv4: pick kv_splits per index stream, not by occupancy alone (#39968)
Co-authored-by: wunhuang <wunhuang@amd.com>
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2026-09-19 11:53:54 -07:00 |
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7b67a96640
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[DSV4] Chunk the indexer MQA logits by query rows under a free-memory budget (#39095)
Signed-off-by: Shiki Wu <shikiw@nvidia.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
|
2026-09-19 11:53:20 -07:00 |
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993d1fccba
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[ROCm] Widen the HiCache JIT copy rounds and enable the K-only host pool (#37152)
Co-authored-by: Xiaobo Chen <xiaobche@smci355-ccs-aus-n05-33.prov.aus.ccs.cpe.ice.amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
|
2026-09-19 08:58:10 -07:00 |
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Xiaoyu Zhang
|
76f9213a41
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[Fix] Keep mHC context out of non-V4 compiled MoE forwards (#40353)
|
2026-09-19 21:41:51 +08:00 |
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Benjamin TruongandXiaoyu Zhang
|
83e29d6c5a
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[perf] Optimize w4a8 MoE for glm5.2 on H200 (#38220)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-19 20:34:25 +08:00 |
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Xiaoyu Zhang
|
7fac84b639
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[DSV4.1] Reduce mHC, metadata and small-batch router overhead (#39704)
|
2026-09-19 19:51:21 +08:00 |
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DarkSharpnessandBBuf
|
d1acbe0746
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[DSV4.1] Big fused wo_a quant (#39957)
Co-authored-by: BBuf <1182563586@qq.com>
|
2026-09-19 19:46:53 +08:00 |
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Xiaoyu Zhang
|
cb22f2451e
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[Cleanup] Deduplicate kernel tests, diffusion fixtures and benchmark helpers (#40265)
|
2026-09-19 19:45:38 +08:00 |
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Xiaoyu Zhang
|
0b0d2c257a
|
[Fix] Repair CI fixtures and ROCm speculative tree device checks (#40325)
|
2026-09-19 18:16:05 +08:00 |
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Cheng Wan
|
3a5f52e144
|
Record a process's placement at publish, not at group build (#40071)
|
2026-09-18 23:52:37 -07:00 |
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Lianmin Zheng
|
5d703de9e4
|
[HiCache] Size MHA host pools from device row width (#40304)
|
2026-09-18 23:37:58 -07:00 |
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Xiaoyu Zhang
|
6533223502
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[Lint] Fix logits processor formatting on main (#40303)
|
2026-09-19 14:31:56 +08:00 |
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Xiaozhu Mengandmxz
|
111aeedd37
|
[Runtime] Add decode CUDA graph hooks for eager logits processing (#40222)
Co-authored-by: mxz <mxz@fb.com>
|
2026-09-18 23:27:03 -07:00 |
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