 YC Yen-Ching Tseng
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72b266d59b
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[AMD] Disable unittest fail-fast for deepseekv4 perf test (#25039)
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2026-05-12 22:47:31 -07:00 |
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Michael
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245f7d8026
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[AMD] Register 5 server-style 1-GPU tests for AMD PR CI (#24572)
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2026-05-12 22:45:52 -07:00 |
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RulinJuiceandRulinJuice
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3f048c80b8
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Reject repetition_penalty=0 in SamplingParams.verify() (#24874)
Co-authored-by: RulinJuice <265952454+RulinJuice@users.noreply.github.com>
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2026-05-12 21:25:23 -07:00 |
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shuwenn
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5ed9a494d0
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[UnifiedTree] fix: allow partial match on evicted+backuped nodes (#24943)
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2026-05-13 11:43:12 +08:00 |
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ZhanghengandJINZ
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6140e45ef3
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[UnifiedTree]: Fix the leaf determination logic in _cascade_evict. (#25068)
Co-authored-by: JINZ <1023553676@qq.com>
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2026-05-13 10:57:32 +08:00 |
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d6d3d0f599
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Optimize SWA memory preallocation for disaggregated decode (#24857)
Co-authored-by: weireweire <weiliangl@nvidia.com>
Co-authored-by: Cheng Wan <chwan@rice.edu>
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2026-05-13 09:09:34 +08:00 |
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Emmanuel AcheampongandClaude Sonnet 4.6
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b49d05fd0e
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feat: add Crusoe managed inference backend (#20475)
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
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2026-05-12 16:23:23 -07:00 |
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Brayden Zhongandb8zhong
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d5f3254ed1
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[Dependency] Flashinfer 0.6.8post1 -> 0.6.11 (#24452)
Co-authored-by: b8zhong <b8zhong@users.noreply.github.com>
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2026-05-12 14:38:32 -07:00 |
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Liangsheng YinandQiaolin Yu
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538832c8b7
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spec: STANDALONE skips hidden_states end-to-end (Optional schema + None-safe consumers) (#25037)
Co-authored-by: Qiaolin Yu <qy254@cornell.edu>
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2026-05-12 12:27:21 -07:00 |
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e86fb42736
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feat: emit per-iteration forward pass metrics via ZMQ PUB (#22789)
Co-authored-by: Ishan Dhanani <ishandhanani@gmail.com>
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: ishandhanani <82981111+ishandhanani@users.noreply.github.com>
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2026-05-12 10:28:17 -07:00 |
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Ma Mingfei
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71285335f7
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Revert "Migrate Intel CPU cases to the test/registered." (#25044)
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2026-05-12 13:32:47 +08:00 |
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jundu
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ecf5d844f5
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Migrate Intel CPU cases to the test/registered. (#22670)
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2026-05-12 13:27:51 +08:00 |
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Ke Bao
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d7f4761a48
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[PD] Refactor hybrid state transfer (#24932)
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2026-05-12 13:16:54 +08:00 |
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Zhangheng
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91907b7b93
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[UnifiedTree]: Fix Unified HiCache tombstone lock release replay (#24972)
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2026-05-12 13:16:06 +08:00 |
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Liangsheng Yin
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f3a8189e20
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[Spec] Internal rename per N2 v2 naming rule (#25014)
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2026-05-11 18:16:26 -07:00 |
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e9dea79755
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(3/n - prefill optimize)[LoRA][MoE] Optimize virtual experts: remove CPU-GPU sync & multi-block CUDA JIT histogram (#24262)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-11 16:36:57 -07:00 |
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Liangsheng Yin
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ce1736fcc6
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[Spec] Remove dead kernel params; fix stale comment in trtllm_mla (#25010)
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2026-05-11 14:50:46 -07:00 |
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Jia Guo
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da0eeb82f2
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perf: add --prefill-only-disable-kv-cache to skip KV pool allocation (#23675)
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2026-05-11 13:10:24 -07:00 |
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Yan Ru Pei
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4b6f776889
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feat(kv-events): publish SWA radix cache events (#24718)
Signed-off-by: PeaBrane <yanrpei@gmail.com>
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2026-05-11 10:31:45 -07:00 |
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TianheandClaude Sonnet 4.6
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95985f983d
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feat(trace): support SGLANG_TRACE_LEVEL env var for startup trace level (#24716)
Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>
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2026-05-11 10:31:03 -07:00 |
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Ke Bao
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36ba60ad49
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Register SWA unit tests under unit/mem_cache (#24974)
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2026-05-11 20:21:05 +08:00 |
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Cheng WanandClaude Opus 4.7
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044bb88a97
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fix: SGLANG_RADIX_FORCE_MISS chunk-cache passthrough (#24950)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-11 00:07:46 -07:00 |
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Bingxu ChenandCursor Agent
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22543b1982
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[AMD] DSv4 nightly hotfix + schedule-aware --continue-on-error in AMD CI (#24825)
Co-authored-by: Cursor Agent <cursoragent@cursor.com>
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2026-05-10 21:46:32 -07:00 |
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d82e339ce2
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[Session R3] Add routed_experts_start_len for absolute routing slice control (#24851)
Co-authored-by: Byron Hsu <byron@periodiclabs.ai>
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: zyzshishui <zyzshishui@gmail.com>
Co-authored-by: Yuzhen Zhou <82826991+zyzshishui@users.noreply.github.com>
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2026-05-10 10:04:43 -07:00 |
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Yuan Luoandluoyuan.luo
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d3fd91ed97
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[Gemma4] Optimize Gemm4 with fused Q/K/V RMSNorm + per-expert FP8 ckpt loader (#24696)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
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2026-05-10 00:24:12 -07:00 |
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ef5e9f8aba
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[DSV4] Cherry pick missing commits from deepseek_v4 branch and enhance tests (#24793)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: yueming-yuan <yym022502@gmail.com>
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2026-05-09 04:15:37 -07:00 |
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Brayden Zhongandb8zhong
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8f33bee31b
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Reland Cute-DSL FP4 dense GEMM (#23590)
Co-authored-by: b8zhong <b8zhong@users.noreply.github.com>
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2026-05-09 02:20:58 -07:00 |
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shuwennandClaude Opus 4.7
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9d12f9e6fa
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[HiCache] ci: lower est_time for test_hicache_spec_file_storage (#24713)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-09 00:33:18 -07:00 |
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Khoa Pham
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1610aa77ab
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Reduce gemma4 moe deterministic test runtime (#24754)
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2026-05-08 20:46:56 -07:00 |
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Liangsheng Yin
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44a527f6f4
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fix patch_torch test queue race (#24739)
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2026-05-08 20:25:59 -07:00 |
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Liangsheng Yin
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1613bae412
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[Spec] Disambiguate verified_id into bonus_token(s) / accept_tokens (#24724)
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2026-05-08 18:24:33 -07:00 |
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d1c5937428
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env: add SGLANG_RADIX_FORCE_MISS to force radix prefix-cache miss (#24726)
Co-authored-by: sihan-zzz <228612289+sihan-zzz@users.noreply.github.com>
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-08 17:46:38 -07:00 |
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YAMY
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560829a171
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feat(scheduler): add adaptive queue-based prefill delayer trigger (#23189)
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2026-05-08 16:54:30 -07:00 |
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YAMY
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6971a03fe6
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fix(fa3): skip scheduler_metadata precompute under DP attention (#24632)
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2026-05-08 16:19:20 -07:00 |
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Niko Ma
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62c2e091f6
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[PD] MORI-IO: Add state transfer, inline transfer model, and high-concurrency fixes (#22665)
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2026-05-08 16:07:22 -07:00 |
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Michael
|
190b15c8fe
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[AMD] Register 8 CPU-bound unit tests for AMD 1-GPU PR CI (#24569)
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2026-05-08 16:01:58 -07:00 |
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Alison Shao
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5fbec0e445
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ci: prune per-commit CUDA tests — move 25 files + 13 testcases to test/manual/ (#24721)
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2026-05-08 15:53:23 -07:00 |
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Jimmy Shongandgemini-code-assist[bot]
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fa8985486e
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[test/fix]: isolate VLM MMMU eval output dirs to fix nightly-4-gpu cross-test pollution (#24623)
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2026-05-08 15:01:53 -07:00 |
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Jimmy Shong
|
096ad02b06
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[Model] Laguna-XS.2 Model Support (#24204)
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2026-05-09 05:43:13 +08:00 |
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Ethan Feng
|
672f778512
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[NemotronH] Fix expert scale weight loading (#24434)
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2026-05-08 12:37:06 -07:00 |
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zhongdaor-nvandzhongdaor-nv
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2cf1a4ab38
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feat: Add KV events for Mamba radix cache (#23678)
Signed-off-by: zhongdaor-nv <220807034+zhongdaor-nv@users.noreply.github.com>
Co-authored-by: zhongdaor-nv <220807034+zhongdaor-nv@users.noreply.github.com>
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2026-05-08 11:53:36 -07:00 |
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Xu Zouandxz-keg
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ca7a8cc61d
|
[Bugfix] Fix a bug causing NVFP4 to be tested on all gpus like SM90 devices. (#24604)
Co-authored-by: xz-keg <xuzou_keg@outlook.com>
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2026-05-08 11:51:30 -07:00 |
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HAI
|
73792629d4
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[AMD] Intro SGLANG_DIFFUSION_AITER_FP8_ATTN (#24677)
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2026-05-08 01:31:00 -07:00 |
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jacky.cheng
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76a1f169b3
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[AMD] Add AMD FP8 MLA attention test for Wan2.2-T2V-A14B (#23955)
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2026-05-08 01:03:51 -07:00 |
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shuwennandQiaolin-Yu
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d9dddd4d7d
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[SPEC V2][2/N] feat: adaptive spec support spec v2 (#23336)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
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2026-05-07 18:33:47 -07:00 |
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+6
|
35870d55ac
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Deepseek V4 (#23882)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Co-authored-by: fzyzcjy <ch271828n@outlook.com>
Co-authored-by: ispobock <ispobaoke@gmail.com>
Co-authored-by: Zhiqiang Xie <xiezhq@stanford.edu>
Co-authored-by: yueming-yuan <yym022502@gmail.com>
Co-authored-by: DarkSharpness <2040703891@qq.com>
Co-authored-by: Yuhao Yang <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: yhyang201 <yhyang201@users.noreply.github.com>
Co-authored-by: yhyang201 <yhyang201@gmail.com>
Co-authored-by: Qiaolin Yu <90088090+qiaolin-yu@users.noreply.github.com>
Co-authored-by: Ethan (Yusheng) Su <11704492+yushengsu-thu@users.noreply.github.com>
Co-authored-by: Mingyi <27337995+wisclmy0611@users.noreply.github.com>
Co-authored-by: Cheng Wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: Yihao Wang <42559837+againstentropy@users.noreply.github.com>
|
2026-05-07 18:32:21 -07:00 |
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Mandepudi Rani ChowdaryandMa Mingfei
|
55224fff08
|
Add Arm64 CPU Phase 1A CI bootstrap (#22123)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-05-08 09:28:23 +08:00 |
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Baizhou Zhang
|
c4bb3ce273
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Fix stuck when enabling MTP on DSA models (#24635)
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2026-05-07 17:06:28 -07:00 |
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Liangsheng Yin
|
95fb722dd2
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Add registry for custom speculative algorithms (#23991)
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2026-05-07 16:11:45 -07:00 |
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Xinyuan Tong
|
5b589ed2e7
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feat(constrained): two-phase reasoning grammar + --enable-strict-thinking (#23953)
|
2026-05-07 14:21:51 -07:00 |
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