 Cheng Wan
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b558cc1abb
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feat(short-conv): shared ShortConvAttnBackend for ZAYA1 CCA + LFM2 short conv (#29867)
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2026-07-01 20:08:00 -07:00 |
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Xinyuan TongandAlison Shao
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0c1a0be3b2
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fix(precision): do not promote failed runs to the comparison baseline (#28190)
Co-authored-by: Alison Shao <54658187+alisonshao@users.noreply.github.com>
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2026-07-01 18:19:15 -07:00 |
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Xinyuan Tong
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cf7c6ac234
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fix(nightly-precision): pin flashinfer allreduce-fusion backend for TP-partial capture contract (#28925)
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2026-07-01 17:26:19 -07:00 |
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Ming Yang
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5ae214f18b
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Extract reusable VMM shareable-handle helpers from register_graph_inputs (#29621)
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2026-07-01 14:02:00 -07:00 |
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YAMYandBaizhou Zhang
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c865347b98
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[DeepSeek V4] Enable FlashMLA sparse prefill by default (#29775)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
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2026-07-01 13:50:05 -07:00 |
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Cheng Wanandlch1475369
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4a8e76805c
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feat(mem_cache): unified memory pool for hybrid Mamba / SWA models (#29678)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
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2026-07-01 13:21:59 -07:00 |
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Michael
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3adfd0f34b
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[AMD] Register 3 unit mem_cache + utils tests for stage-b-test-1-gpu-small-amd (#29782)
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2026-07-01 12:57:48 -07:00 |
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Michael
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8361561c24
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[AMD] Fix int8 per-token quant Triton portability + register test for AMD nightly CI (#29694)
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2026-07-01 12:56:33 -07:00 |
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Zhihao Wang
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779ea4a9b5
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[RL] fix deepseek v4 MXFP8 flashinfer_trtllm_routed MoE weight update (#28676)
Signed-off-by: zhihaow6 <zhihaow6@illinois.edu>
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2026-07-01 12:29:08 -07:00 |
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eb75d990f7
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[Bugfix] compressed-tensors WNA16 MoE: don't assume a "Linear" config group (#29761)
Signed-off-by: Joe Rowell <joerowell4@gmail.com>
Co-authored-by: Jiminator <jimmysh341@gmail.com>
Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com>
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2026-07-01 18:08:09 +00:00 |
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Kangyan-ZhouandClaude Opus 4.8
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30c9801b39
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[disagg] Fix KV-event publisher port collision under pure data parallelism (#29211)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2026-07-01 10:57:34 -07:00 |
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YC Yen-Ching Tseng
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2a6e5c60fe
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[AMD] Rebalance stage-c-large-8-gpu-mi35x partitions to fix 60-min timeout (#29726)
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2026-07-01 08:17:00 -07:00 |
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13dc5f2dc7
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[HiCache][AMD] Add UMBP tiered DRAM + SSD L3 storage backend with hugepage host allocator (#25377)
Co-authored-by: TianDi101 ditian12@amd.com
Co-authored-by: Niko Ma nima@amd.com
Co-authored-by: Wu, Yutong yutong.wu@amd.com
Co-authored-by: figo fizhang@amd.com
Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-07-01 22:21:37 +08:00 |
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Mohammad Miadh Angkad
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a0d9791810
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[CI] Fix fused EH norm CI registration (#29845)
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2026-07-01 21:27:07 +08:00 |
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Lukas Humbel
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7d9de81cda
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feat(hicache): Use NIXL path-mode (#27060)
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2026-07-01 02:59:45 -07:00 |
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Mohammad Miadh Angkad
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07ca24372b
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Add fused EH norm for DeepSeek NextN (#29667)
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2026-07-01 02:46:21 -07:00 |
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Daniel Stokes
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8ee200972e
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[fix] Add support for flashinfer MOE A2A to Qwen3 BF16 model path (#26255)
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2026-07-01 01:59:54 -07:00 |
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ashwini rathiandSinghal, Shubham
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5134dcdcab
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[Intel XPU] Initially add nightly GSM8K accuracy tests for Llama-3.1-8B (TP=2) and Qwen3-32B (TP=4) (#28908)
Co-authored-by: Singhal, Shubham <shubham.singhal@intel.com>
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2026-07-01 16:27:24 +08:00 |
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Bingxu Chen
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548f505cc5
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[AMD] Cover DeepSeek-R1 MXFP4 TP4 MTP nightly CI (#29290)
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2026-07-01 01:21:17 -07:00 |
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Michael
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69ce72020a
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[AMD] Register ltx2_ada_values JIT kernel test for AMD nightly CI (#29693)
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2026-07-01 01:13:55 -07:00 |
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huangtingwei
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5e1ccd9320
|
[HiCache] Optimize HiCache hash generation with bulk token byte conversion (#28287)
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2026-07-01 15:44:23 +08:00 |
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df0dfbaa45
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[Kernel] Strengthen kernel shape coverage (#29636)
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-07-01 15:44:20 +08:00 |
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YC Yen-Ching Tseng
|
308d89e042
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[AMD] Split qwen3.5 triton DCP test into its own nightly job (#29409)
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2026-07-01 00:39:39 -07:00 |
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Jialin Ouyang
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40594bd381
|
[passthrough] engine: zstd request-body decompression + header overrides (#29684)
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2026-06-30 23:48:56 -07:00 |
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Xiaoyu Zhang
|
fcb9f229b3
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[KDA-Pilot] Add LTX2 QKNorm split-RoPE CUDA fast path (#29708)
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2026-07-01 14:42:07 +08:00 |
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Chang Min Bark
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41779d56fd
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fix: make write_token dynamic (#29271)
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2026-06-30 22:55:57 -07:00 |
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Lijuan Tang
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3cdc2415b1
|
[MLX] Fix step-bounded profiling for bench tools on Apple Silicon (#29217)
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2026-06-30 22:55:29 -07:00 |
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zhangxiaolei
|
56f22cd520
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Optimize C128 state pool allocation using request state pool (#28612)
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2026-06-30 19:11:29 -07:00 |
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|
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53c61bd5e6
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[bug2] skip swa recovery on locked full kv (#29352)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
|
2026-06-30 16:07:06 -07:00 |
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Feng Yaoandispobock
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1c2523b719
|
[bug1] keep full kv when swa skips leaf data (#29351)
Co-authored-by: ispobock <ispobaoke@gmail.com>
|
2026-07-01 00:51:18 +08:00 |
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|
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cf36dca6d4
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[JIT Kernel] Triton moe fused gate (#25835)
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: ziyi.xu <ziyi.xu@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-06-30 23:26:18 +08:00 |
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|
Stanley Winata
|
a5e6dd3767
|
[AMD] Implement QuarkW4A8MXFp4MoE to support amd/gpt-oss-120b-w-mxfp4-a-fp8 (#27204)
Signed-off-by: Stanley Winata <stanley.winata@amd.com>
|
2026-06-30 01:24:22 -07:00 |
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Mohammad Miadh Angkad
|
b6fceaa789
|
[DSA] Use cos_sin_cache for DSA indexer fusion (#29613)
|
2026-06-29 23:49:00 -07:00 |
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|
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dbb51c46ac
|
[CI] Migrate JIT tests missed by #29066 to runner_config registration (#29715)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
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2026-06-29 23:21:14 -07:00 |
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Zhangheng
|
dad0120c57
|
[HiSparse]: Skip flaky hisparse-nixl ci (#29710)
|
2026-06-30 14:04:34 +08:00 |
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|
Baizhou Zhang
|
cc238270b1
|
Update GLM tests to 5.2 and delete redundant tests (#29686)
|
2026-06-29 23:04:26 -07:00 |
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YC Yen-Ching Tseng
|
7d9116d9d7
|
Fix test_type_based_dispatcher after TokenizedGenerateReqInput field changes (#29376)
|
2026-06-29 22:22:22 -07:00 |
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Michael
|
7da4e30d9b
|
[AMD] Register fused_metadata_copy JIT kernel test for AMD nightly CI (#29671)
|
2026-06-29 21:26:11 -07:00 |
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Zhaoyi Liandbingxche
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6bf15aa2b9
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[AMD]: Enable NIXL PD disaggregation for ROCm(1/n) (#28348)
Co-authored-by: bingxche <bingxche@amd.com>
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2026-06-29 21:23:09 -07:00 |
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Mohammad Miadh Angkad
|
3a72d02415
|
[DSA] Optimize DSA CUDA graph replay metadata generation (#29499)
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2026-06-29 19:53:23 -07:00 |
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|
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3e16be2122
|
[CI] Migrate JIT tests to runner config registration (#29066)
Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-29 19:12:14 -07:00 |
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Ho-Ren (Jack) Chuang
|
bc8b3ab1f5
|
[Kernel] Add SM90 Q8KV8 FP8 Sparse MLA Prefill JIT Kernel with Tests and Benchmark (#25751)
|
2026-06-30 09:00:11 +08:00 |
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Ho-Ren (Jack) Chuang
|
a6bc432fd8
|
[Perf][Kernel] Fuse SiLU+Mul into NVFP4 Expert Quantization for CUTLASS MoE (#18612)
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2026-06-29 16:51:01 -07:00 |
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eeechoandAliceChenyy
|
f0bf96390b
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[SM120] Add FlashInfer sparse MLA decode for DSv4-Flash (#27455)
Co-authored-by: AliceChenyy <alicechenyy@users.noreply.github.com>
|
2026-06-29 16:27:16 -07:00 |
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Trevor Morris
|
b8c25bfaa7
|
[NVIDIA] Support flashinfer a2a with flashinfer_trtllm_routed moe (#22394)
|
2026-06-29 16:23:58 -07:00 |
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Cheng Wanandlch1475369
|
fc96edd297
|
feat(mem_cache): page-major (layer-major within a page) KV/state layout (#29533)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
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2026-06-29 14:49:54 -07:00 |
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Mohammad Miadh Angkad
|
6c018eb4d1
|
Fix bounded checkpoint prefetching and buffered drop-cache handling (#29156)
|
2026-06-29 21:49:16 +00:00 |
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|
Feng Yao
|
e6c15f76f3
|
[optimize] fix swa eviction boundary for unfinished inserts (#29350)
|
2026-06-30 00:19:15 +08:00 |
|
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Jyothirmai KottuandXinyuan Tong
|
473a278dd1
|
model: support nvidia/LocateAnything-3B (#28958)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-06-30 00:16:42 +08:00 |
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Shangming Cai
|
93926b9a95
|
Add Qwen3 MoE tests for PP compatibility with CP and DP (#29640)
Signed-off-by: Shangming Cai <csmthu@gmail.com>
|
2026-06-29 18:52:03 +08:00 |
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