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Author SHA1 Message Date
WenhaoZhang 395a2201e4 [diffusion] rl: enable RL rollout path for LTX-2.3 post-training (#28926) 2026-07-09 10:24:06 +08:00
Chetan Kumar VermaClaude Opus 4.8gemini-code-assist[bot]Ma Mingfei
 		6bce72d968 [Intel GPU] xpu_piecewise: fall back to eager when PCG capture stream is unset (#30235) 
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
 2026-07-09 10:21:43 +08:00
Baizhou Zhang 2b3d9ad375 [Tiny] Fix docstring in CP abstractions (#30579) 2026-07-08 18:41:40 -07:00
cen121212 0ffed946f2 [NPU] Add extra topk_weights input in deepep ll dispatch (#29480) 2026-07-09 09:23:29 +08:00
Michael cf8f1df6e8 [AMD] add dedicated jit-kernel-benchmark-test-amd stage + register portable JIT benches (#30307) 2026-07-08 18:09:05 -07:00
Xinyuan Tong 074bb928f0 Move template manager files under parser; update CODEOWNERS (#26052) 2026-07-08 16:47:36 -07:00
fzyzcjy bc607ff650 Enhance mechanical refactor proof construction and verification skill (#30483) 2026-07-09 07:39:11 +08:00
fzyzcjy 6af1d5ff2d Enhance large class styles and code styles (#28978) 2026-07-09 07:32:03 +08:00
Xinyuan Tong 937734d3ed ci(nightly): add force_baseline_update dispatch input for precision job (#30495) 2026-07-08 16:27:41 -07:00
Cheng WanandClaude Opus 4.8 cc13e2eae7 [CI] Move piecewise CUDA graph (pcg) tests to nightly (#30563) 
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-08 16:07:08 -07:00
Liangsheng Yin 8f9307736a [misc] Add CI-only guards for the FutureMap seq_lens relay (#30471) 2026-07-08 15:29:53 -07:00
cctry 096551eed6 Make CUDA graph disabling PD-role-aware (prefill/decode) (#30409) 2026-07-08 15:08:22 -07:00
wangjiaxin99zhaolinRaiden-MakotoHAI
 		07ef650ef7 [AMD] Fix GLM-5.2 MTP Quark excludes (#30265) 
Co-authored-by: zhaolin <zhaolin@amd.com>
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: HAI <hixiao@gmail.com>
 2026-07-08 14:57:10 -07:00
Connor CarpenterandIshan Dhanani cc7d6659fd feat(grpc): support disaggregated generation requests (#30440) 
Signed-off-by: Connor Carpenter <connorc@nvidia.com>
Co-authored-by: Ishan Dhanani <ishandhanani@gmail.com>
 2026-07-08 14:53:56 -07:00
Lianmin Zheng ca8f15cd70 Fix FlashInfer A2A IMA by DP-synchronizing the decode graph bucket (#30242) (#30450) 2026-07-08 14:34:49 -07:00
Michael c55190a638 [AMD] Register 2 CPU-bound 1-GPU tests (phase_checker, scripted_runtime_core) for AMD PR CI (#30446) 2026-07-08 14:04:23 -07:00
Liangsheng Yin 10e7f2925f [Fix] Chain the seq_lens publish event records so prebuilt seeding keeps the forward fence (#30435) 2026-07-08 13:43:09 -07:00
Michael 47a6dfd708 [AMD] Register 3 ROCm-portable JIT kernel tests for AMD CI (#30212) 2026-07-08 13:38:17 -07:00
Xinyuan TongandEazyReal 45019b56ce [Bugfix] Map reasoning_effort=low to Nemotron-3 Super low_effort + warn on unsupported levels (#30463) 
Co-authored-by: EazyReal <8047065+EazyReal@users.noreply.github.com>
 2026-07-08 12:19:44 -07:00
sonle5andsunxxuns 8d2b66fd90 Fix gfx95 bpreshuffle FP8 activation scale layout (#29275) 
Co-authored-by: sunxxuns <126995791+sunxxuns@users.noreply.github.com>
 2026-07-08 10:55:09 -07:00
YC Yen-Ching Tseng fc378f843e [AMD] Temporarily reduce AMD scheduled test frequency to save resource (#30534) 2026-07-08 09:30:59 -07:00
Mohammad Miadh Angkad 04e4fadff3 Use FP32 logits in MoEGate fallbacks (#30323) 2026-07-08 23:43:45 +08:00
Xiaoyu Zhang b8ca06fdad Fix zero expert routed ids for MoE backends (#30387) 2026-07-08 21:23:25 +08:00
shuwenn 108a183f6b [mem_cache][6/N] refactor: move MHA host-pool into pool_host/mha.py (#30249) 2026-07-08 20:12:52 +08:00
Jimmy ShongandClaude Opus 4.8 4c5fe42be4 [DSA] Fix IMA in fused top-k v2: write all output slots on tie overflow (#30512) 
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
 2026-07-08 19:49:26 +08:00
HuangJi 3d96bb9721 [diffusion] chore: rename lingbot world v2 (#30518) 2026-07-08 19:06:44 +08:00
amote-i 042228a195 [NPU] [DOC] Remove unsupported options of features on Ascend NPU (#30504) 2026-07-08 17:35:06 +08:00
jacky.cheng 96368a5f77 [AMD] Fuse shared-expert sigmoid + bf16->fp32 cast into the MoE append kernel (3 kernels -> 1) (#28658) 2026-07-08 02:34:20 -07:00
YC Yen-Ching Tseng 669b4bc72b [AMD] Gate stage-c on stage-b-test-1-gpu-large-amd (#30496) 2026-07-08 15:41:21 +08:00
YAMY 8a868f8c00 [NVIDIA] Allow modelopt_mixed quantization with flashinfer_cutedsl MoE runner (#30443) 2026-07-07 23:50:52 -07:00
Mohammad Miadh Angkad fda87173ab Revert "Increase the KV cache pool when using indexShare by 15% (#30310)" (#30472) 2026-07-07 23:48:35 -07:00
Xiaoyu ZhangBBufClaude Opus 4.8BBuf
 		33c3dfd7e0 [diffusion] Enable breakable CUDA graph (BCG) for diffusion DiTs (#27436) 
Co-authored-by: BBuf <xiaoyu.zhang@radixark.net>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: BBuf <bbuf@sglang.local>
 2026-07-08 14:45:48 +08:00
amote-i c9303a08da Fix scheduler crash on prefill-unreachable decode abort (#29834) 2026-07-08 14:06:37 +08:00
Cheng Wan 7709a1f358 [refactor] ctx.resources: named slots, stream leases, and workspace buffer leases (#30348) 2026-07-07 21:30:10 -07:00
Cheng Wan b7cca0bf8f [refactor] Collect MoE and DP-attention runtime state into typed flag groups (#30347) 2026-07-07 21:29:27 -07:00
Cheng Wan be32c57598 [refactor] Read resolved config from server_args fields; retire the flags mirror tier (#30346) 2026-07-07 21:28:34 -07:00
Cheng Wan b14f7b4f75 [refactor] Move model-capability adjustments into the resolution pipeline (#30299) 2026-07-07 21:26:55 -07:00
Rahul VijayaraghavanandMa Mingfei d4963f5c55 Fix prefill CUDA graph disabled for deeply-nested multimodal models (#30006) 
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
 2026-07-08 12:11:58 +08:00
Brayden ZhongandBrayden Zhong 455ab36eeb Increase the KV cache pool when using indexShare by 15% (#30310) 
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
 2026-07-07 20:59:13 -07:00
weireweireandweireweire c7ca332fb0 Fix DSV4 prefill large Triton recompilation idle across context lengths (#30255) 
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
 2026-07-07 20:35:33 -07:00
Baizhou Zhang fa278a762c Fix FA3 prefill CP NaNs (#30439) 2026-07-07 20:16:09 -07:00
Alison Shao f3c3eea608 ci: make multi-GPU jit test hangs attributable from the CI log (#29925) 2026-07-07 19:56:32 -07:00
ThanhhaoHao PhanClaude Opus 4.8
 		7bc343470f [Spec] DFlash: support pure-MLA targets with an fp8 KV cache (Kimi-K2.x-NVFP4) (#29218) 
Co-authored-by: Hao Phan <htphan@nvidia.com>
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-07 19:52:14 -07:00
HuangJi db40fd83d2 [diffusion] model: support LingBot-World 2.0 (#30361) 2026-07-08 10:42:50 +08:00
Yihao WangandClaude Opus 4.8 68901ba387 [diffusion] Support SP for Krea-2 (#29777) 
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-07 19:39:00 -07:00
YC Yen-Ching Tsengandbingxche 9bf122a455 [AMD] Run MI355X disaggregation Nightly Test with runtime checkout code mechanism (#30386) 
Co-authored-by: bingxche <bingxche@amd.com>
 2026-07-08 09:27:49 +08:00
Yuchen Tian 9f5948c391 feat(mem_cache): add client-side metadata cache for HiCacheFile storage (#29716) 2026-07-07 18:21:46 -07:00
Yuwei AnandClaude Opus 4.8 49109d4267 [Tiny] Fix Import Error for Pure TP config with flashinfer_mxfp4 (#30426) 
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
 2026-07-07 18:17:52 -07:00
Chi McIsaacandMick fa185ed84d [diffusion] fix: fix z-Image accuracy (#29742) 
Co-authored-by: Mick <mickjagger19@icloud.com>
 2026-07-08 09:08:32 +08:00
Kaixiliqichaochenbong
 		d7dcdf3efd [DSV4] perf: Make FP8 quant output tensor contiguous (#27926) 
Co-authored-by: liqichao <liqichao@baidu.com>
Co-authored-by: chenbong <bhchen@stu.xmu.edu.cn>
 2026-07-07 17:40:59 -07:00