 Ke Bao
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372a893744
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Move deferred mamba cow and clear (#29945)
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2026-07-03 11:29:05 +08:00 |
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Xiaoyu ZhangandClaude Opus 4.8
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a2d7eb303e
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[MoE] Consolidate ungrouped + grouped gate/topk onto one Triton router (#26771) — faster than AOT on B200/H100/H200, at parity with flashinfer (#29771)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
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2026-07-03 11:18:59 +08:00 |
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Michael
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bee0f34e68
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[AMD] Accept ROCm tensors in JIT kernel TensorMatcher + register 4 kernel tests (#29822)
|
2026-07-02 19:29:47 -07:00 |
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YC Yen-Ching Tseng
|
05bc3f2aa7
|
[AMD] Gate broken CK block-FP8 GEMM shapes to aiter-triton-GEMM to fix ROCm 7.0 Qwen3.5 accuracy (#29918)
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2026-07-02 18:18:37 -07:00 |
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Po-Han Huang (NVIDIA)
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17cce6a85f
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Fix shared logits buffer for reduced-vocab draft models (#29943)
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2026-07-02 16:08:56 -07:00 |
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Michael
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8519be82e8
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[AMD][DeepSeek V4] Fix default FlashMLA sparse prefill off on ROCm/HIP (#29982)
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2026-07-02 16:00:09 -07:00 |
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Oxana Korzh
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f3904f0293
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[bugfix][AMD] Disable aiter allreduce+RMSNorm fusion under DP attention / EP (#27835)
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2026-07-02 15:31:25 -07:00 |
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YukioZzzandDuyi-Wang
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caf2e5da2d
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[AMD] Fix MiniMax M3 state transfer in Mori PD (#29756)
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
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2026-07-02 15:02:10 -07:00 |
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Rain Jiang
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ae1f0c6d07
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session_id dataclass field should not put in msgpack struct (#29977)
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2026-07-02 14:10:12 -07:00 |
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Mohammad Miadh Angkad
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cfb9c574d3
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Fix UE8M0 scale rounding for DeepGEMM (#29956)
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2026-07-02 13:42:17 -07:00 |
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Cheng Wanandlch1475369
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bc25abb786
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perf(triton): avoid per-step D2H .item() sync in cuda-graph loc translate (#29921)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
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2026-07-02 13:20:00 -07:00 |
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Zhiqiang Xie
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f19246e59a
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[HiCache] write_back policy refinement (#29817)
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2026-07-02 12:16:03 -07:00 |
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Brayden ZhongandBrayden Zhong
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1b6d1e9752
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Fix wrong RMSNorm fallback to old Flashinfer CUDA kernel when in PCG (#29702)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
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2026-07-03 00:49:49 +08:00 |
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Xinyuan Tong
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9588cacaa1
|
Remove transformers 5.12.1 dead-code workarounds (#29758)
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2026-07-03 00:03:06 +08:00 |
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McZyWu
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c05c48b35e
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bugfix for npu Grok2 model --detokenizer without all special ids (#29853)
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2026-07-02 22:12:48 +08:00 |
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McZyWu
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bdd3515389
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NPU case rl update weights for tensor load_format == None and flatten bucket (#29503)
|
2026-07-02 22:12:05 +08:00 |
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Ke Bao
|
a375e9f3da
|
Fix SWA eviction tombstoning the last leaf (#29860)
|
2026-07-02 21:42:30 +08:00 |
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Mick
|
3c1adddff9
|
[diffusion] refactor: refactor cuda attention backend resolver (#29852)
|
2026-07-02 21:34:54 +08:00 |
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Mick
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119b76567d
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[diffusion] feat: add --offload-during-compile to fit max-autotune on tight-memory GPUs (#29862)
|
2026-07-02 19:39:19 +08:00 |
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26b15a0825
|
[LFM2-MoE] Support Transformers v5 packed MoE expert weights (#29659)
Co-authored-by: Piotr Mazurek <piotr.mazurek@liquid.ai>
Co-authored-by: Changyi Yang <changyiyang2023@gmail.com>
|
2026-07-02 17:13:02 +08:00 |
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Xiaoyu Zhang
|
b276a9acee
|
chore: cleanup garbage code (#29770)
|
2026-07-02 16:14:01 +08:00 |
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cctry
|
697b400d70
|
Share one logits output buffer across prefill/decode/draft cuda-graph runners (#29779)
|
2026-07-01 23:30:56 -07:00 |
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|
Cao E
|
926140d789
|
[XPU] Enable XPU graph support (decode full-graph + prefill tc_piecewise) (#29053)
|
2026-07-02 13:24:35 +08:00 |
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|
ANSHUMAN TRIPATHY
|
4fffc6448b
|
Speculative decoding support on XPU (#23180)
|
2026-07-02 13:23:24 +08:00 |
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|
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790156c98f
|
[Intel GPU] DeepSeek V4 7/N: Support fused_rope_inplace on XPU using triton (#27915)
Signed-off-by: P V R K Jyothendra Varma <polisettyvarma@gmail.com>
Co-authored-by: Rahul Vijayaraghavan <rahul.vijayaraghavan@intel.com>
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-07-02 13:22:20 +08:00 |
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Zaili Wang
|
cb06c4e6ce
|
[CPU] Fix model failures on Xeon (#29497)
|
2026-07-02 13:20:18 +08:00 |
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|
Zaili WangandMa Mingfei
|
aff44d748d
|
[CPU] Padding for dim divisibility in TP3/6 cases (#20072)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
|
2026-07-02 13:14:39 +08:00 |
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cctry
|
80ac11eda3
|
Fix capture-mode detection during breakable CUDA graph capture (#29866)
|
2026-07-01 22:12:56 -07:00 |
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|
sushil Dubey
|
e88645d65f
|
[amd][diffusion] fix: fix causal Conv3D cat/pad fusion crashes for wan2.2 t2v (#29672)
Signed-off-by: Sushil Dubey <sushilghansyam.dubey@amd.com>
|
2026-07-02 13:11:30 +08:00 |
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Yuwei An
|
0543246184
|
Enable Breakable Cuda Graph as Default (#29458)
|
2026-07-01 22:04:44 -07:00 |
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|
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d15b79e96e
|
[bug6] clear stale mamba cow source on rematch (#29354)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Hanming Lu <hanminglu@meta.com>
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
|
2026-07-02 13:04:09 +08:00 |
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YAMYandYuwei An
|
307094dc7d
|
[DeepSeek V4] Cover both dense and sparse prefill paths in the compress attention unittest (#29885)
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
|
2026-07-01 21:20:12 -07:00 |
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|
Feng Yao
|
e6f6a353bf
|
pad customized_info for mixed output batches (#29842)
|
2026-07-02 12:07:58 +08:00 |
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|
Yuan Luoandluoyuan.luo
|
eb23f9a86b
|
[KDA] Add FlashKDA prefill backend for safe-gate KDA linear attention (#29472)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
|
2026-07-02 11:37:04 +08:00 |
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|
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6eeb9871e5
|
Add Laguna XS.2.1 DFlash support to SGLang (#29446)
Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
|
2026-07-01 20:26:23 -07:00 |
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|
Estrella-xx
|
bac351d617
|
[NPU] Fix block_table batch size mismatch in GLM-4.7-Flash DeepEP + MTP without CUDA Graphs (#29829)
|
2026-07-02 11:09:01 +08:00 |
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|
Cheng Wan
|
b558cc1abb
|
feat(short-conv): shared ShortConvAttnBackend for ZAYA1 CCA + LFM2 short conv (#29867)
|
2026-07-01 20:08:00 -07:00 |
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|
iridiumine
|
70df09b833
|
Fix MambaPool.clear_slots OOM by replacing expand-based tensor allocation with scalar zeroing (#27923)
|
2026-07-02 09:26:55 +08:00 |
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|
Xinyuan TongandAlison Shao
|
0c1a0be3b2
|
fix(precision): do not promote failed runs to the comparison baseline (#28190)
Co-authored-by: Alison Shao <54658187+alisonshao@users.noreply.github.com>
|
2026-07-01 18:19:15 -07:00 |
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|
Ming Yang
|
5ae214f18b
|
Extract reusable VMM shareable-handle helpers from register_graph_inputs (#29621)
|
2026-07-01 14:02:00 -07:00 |
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|
YAMYandBaizhou Zhang
|
c865347b98
|
[DeepSeek V4] Enable FlashMLA sparse prefill by default (#29775)
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
|
2026-07-01 13:50:05 -07:00 |
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|
Mohammad Miadh Angkad
|
8f0d320d31
|
[Spec] Enable FlashInfer autotune for spec draft (#29595)
|
2026-07-01 13:36:07 -07:00 |
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Cheng Wanandlch1475369
|
4a8e76805c
|
feat(mem_cache): unified memory pool for hybrid Mamba / SWA models (#29678)
Co-authored-by: lch1475369 <lch1475369@gmail.com>
|
2026-07-01 13:21:59 -07:00 |
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|
Michael
|
8361561c24
|
[AMD] Fix int8 per-token quant Triton portability + register test for AMD nightly CI (#29694)
|
2026-07-01 12:56:33 -07:00 |
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|
Baizhou Zhang
|
c312cdd3a7
|
Upgrading tvm-ffi/sgl-deep-gemm/tilelang (#29554)
|
2026-07-01 12:32:18 -07:00 |
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|
Zhihao Wang
|
779ea4a9b5
|
[RL] fix deepseek v4 MXFP8 flashinfer_trtllm_routed MoE weight update (#28676)
Signed-off-by: zhihaow6 <zhihaow6@illinois.edu>
|
2026-07-01 12:29:08 -07:00 |
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|
|
eb75d990f7
|
[Bugfix] compressed-tensors WNA16 MoE: don't assume a "Linear" config group (#29761)
Signed-off-by: Joe Rowell <joerowell4@gmail.com>
Co-authored-by: Jiminator <jimmysh341@gmail.com>
Co-authored-by: Jimmy Shong <69131491+Jiminator@users.noreply.github.com>
|
2026-07-01 18:08:09 +00:00 |
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|
Kangyan-ZhouandClaude Opus 4.8
|
30c9801b39
|
[disagg] Fix KV-event publisher port collision under pure data parallelism (#29211)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-07-01 10:57:34 -07:00 |
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|
Mick
|
03b9278da0
|
[diffusion] CI: tighten multimodal-gen consistency thresholds (#29824)
|
2026-07-02 01:32:51 +08:00 |
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|
|
13dc5f2dc7
|
[HiCache][AMD] Add UMBP tiered DRAM + SSD L3 storage backend with hugepage host allocator (#25377)
Co-authored-by: TianDi101 ditian12@amd.com
Co-authored-by: Niko Ma nima@amd.com
Co-authored-by: Wu, Yutong yutong.wu@amd.com
Co-authored-by: figo fizhang@amd.com
Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-07-01 22:21:37 +08:00 |
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