 Pranjal Shankhdharandpranjalssh
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35df2fecde
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[Fix] Stamp sequence-parallel state on dummy forward batches (#38564)
Co-authored-by: pranjalssh <pranjalssh@fb.com>
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2026-09-09 01:03:03 -07:00 |
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Yuhao Yang
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13469c16d3
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Store mamba prefix-cache checkpoints at the configured SSM state dtype (#34820)
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2026-09-09 15:25:57 +08:00 |
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Ankith AverineniandHaiShaw
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eb42598bdd
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[AMD][DSV4] Skip the paged SWA page return under the per-request ring (#38571)
Co-authored-by: HaiShaw <hixiao@gmail.com>
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2026-09-08 21:15:30 -07:00 |
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Xiaoyu Zhang
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2952c8d5ea
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[Diffusion] Fuse LongCat Image normalization and modulation (#38530)
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2026-09-09 11:12:17 +08:00 |
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Jialin Ouyang
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7a464a7014
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[Rust TreeCore] Harden runtime and CI parity (#37303)
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2026-09-09 10:40:22 +08:00 |
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DayuxiaoshuiandXiaoyu Zhang
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db1de6ff4c
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[Diffusion] Keep the Wan VAE decoder channels_last and add a Triton NHWC nearest upsample (#38182)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-09 09:31:35 +08:00 |
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295132c4a5
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[NPU] Add sparsity-driven KV offload for DeepSeek DSA on Ascend (#33089)
Co-authored-by: itcj <itcj@foxmail.com>
Co-authored-by: chenyh <chenyh18@mail.ustc.edu.cn>
Co-authored-by: hibikid <7514545+hibikid@user.noreply.gitee.com>
Co-authored-by: Chengjie Tang <tangcj@sxu.edu.cn>
Co-authored-by: wangbiao0814 <wangbiao0814@outlook.com>
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2026-09-09 09:13:22 +08:00 |
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Cheng Wan
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db272201a2
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[Config] Retire get_global_server_args, and clear the deprecated flags that have a replacement (#38375)
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2026-09-08 16:42:12 -07:00 |
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Baizhou Zhang
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ed183d45ac
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[CP V1 Deprecation 4/5] Canonicalize prefill CP API names (#36229)
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2026-09-08 16:03:36 -07:00 |
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+3
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52fecfdf09
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support qwen 3.8 flash next (#37500)
Co-authored-by: ch-wan <54331508+ch-wan@users.noreply.github.com>
Co-authored-by: ispobock <26454835+ispobock@users.noreply.github.com>
Co-authored-by: JustinTong0323 <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: samuellees <26428561+samuellees@users.noreply.github.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: yhyang201 <47235274+yhyang201@users.noreply.github.com>
Co-authored-by: yizhang2077 <25844240+yizhang2077@users.noreply.github.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: Shinto C V <cshintov@gmail.com>
Co-authored-by: Julian Huang <huangzhilin.hzl@antgroup.com>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
Co-authored-by: yhyang201 <yhyang201@gmail.com>
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2026-09-08 13:56:21 -07:00 |
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Brayden ZhongandBrayden Zhong
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30e7a3072d
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Keep fp32 routing weights in the fp8 block-scale and bf16 trtllm MoE (#33631)
Co-authored-by: Brayden Zhong <brayden@radixark.ai>
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2026-09-08 08:56:40 -07:00 |
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HZYandZhangheng
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8a0863c728
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[HiCache] Add MLA host-dedup primitives (#36800)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-08 23:40:21 +08:00 |
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Liu Ziming
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beecfda314
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[observability] Fix missing e2e/decode/inference latency span attributes (#37789)
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2026-09-08 22:50:55 +08:00 |
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HZY
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a6b542813f
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fix(glm-5.2-nvfp4): bound Mooncake synchronous transfer batches (#32758)
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2026-09-08 22:14:33 +08:00 |
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SovietPowerandXiaoyu Zhang
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4df5df911b
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[Scheduler] Add HRRN schedule policy to significantly reduce TTFT (#32911)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-08 22:14:03 +08:00 |
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Po-Han Huang (NVIDIA)
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5097f9ac95
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Disable Hopper GLM shared-expert fusion for modelopt_fp4 Marlin (#37325)
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2026-09-08 06:16:36 -07:00 |
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pllimax
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2d339ddef1
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[NPU] Phase A calibration: full GSM8K eval for dp_attention mixed-chunk (#38422)
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2026-09-08 21:14:48 +08:00 |
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Xiaoyu Zhang
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554f817948
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[Diffusion] Optimize LTX-2 QKNorm and split RoPE on Hopper (#38396)
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2026-09-08 19:05:02 +08:00 |
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amd-danli103
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141febf329
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[AMD] fix: use the hardware fp8 e4m3 convert on gfx950 (#37140)
Signed-off-by: amd-danli103 <danli103@amd.com>
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2026-09-08 03:01:53 -07:00 |
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vorapolsiloai
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7edcdd5ae6
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[AMD] Skip AITER FP8 ASM prefill when GQA is unsupported (#38467)
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2026-09-08 02:49:47 -07:00 |
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Sage
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5aab054ec8
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[rust-server] fix p/d bootstrap across dp listeners (#36234)
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2026-09-08 13:22:32 +08:00 |
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Shuwen Wang
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da1c017ae8
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[CI] test: initialize disable_radix_cache in scheduler stub (#38418)
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2026-09-08 13:15:47 +08:00 |
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Anupa Sajikumar
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91a45ea37e
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[Intel][XPU][LoRA] Enable LoRA on Intel XPU (#30345)
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2026-09-08 12:46:41 +08:00 |
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Liangsheng Yin
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28ebede865
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[mem_cache] Free hybrid SWA pages by one representative per page on page_size > 1 (#38159)
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2026-09-07 20:15:54 -07:00 |
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Liangsheng Yin
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b23d835048
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[Scheduler] Unify per-iteration request intake into ingest_requests() (#38389)
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2026-09-07 20:02:02 -07:00 |
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EdwardXuyandEdwardXuy
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7d2d6624b1
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[NPU] Enable L1 prefix cache for Kimi-K3 W4A8 accuracy test (gpqa) (#38125)
Co-authored-by: EdwardXuy <EdwardXuy@users.noreply.github.com>
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2026-09-08 10:39:58 +08:00 |
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Polisetty V R K Jyothendra Varma
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cf35384fe4
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[Intel GPU] Add MLA support to Intel XPU Attention backend for Prefill (#35866)
Signed-off-by: P V R K Jyothendra Varma <polisetty.v.r.k.jyothendra.varma@intel.com>
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2026-09-08 10:29:28 +08:00 |
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HZY
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8656901504
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[Fix][DSA] Bound prefill Triton specializations for page-table stride (#37093)
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2026-09-08 10:23:51 +08:00 |
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Chao Shiandhuangtingwei9988
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e31e5319a0
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HiCache: Reduce the number of all_reduce in check_hicache_events for PP (#37562)
Co-authored-by: huangtingwei9988 <huangtingwei.htw@antgroup.com>
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2026-09-08 10:13:22 +08:00 |
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Siju Samuel
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2358916d5a
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[Feature][Intel XPU] Add memory saver support for Intel XPU via upstream torch_memory_saver (#29935)
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2026-09-08 09:38:51 +08:00 |
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qyb233
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c72cae201e
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[NPU] Fix ViT graph key layout handling (#37758)
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2026-09-08 09:21:02 +08:00 |
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5aa913e156
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[AMD][GLM-5.2] Keep GlmMoeDsa MoE e_score_correction_bias in fp32 (#37133)
Co-authored-by: JohnQinAMD <yanyuan.qin@amd.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Zhang, Jiejing <jiejing.zhang@amd.com>
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2026-09-07 18:17:54 -07:00 |
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Kamil
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792543f98c
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[Scheduler] Make request-timeout aborts rank-consistent to fix TP collective hangs (#37143)
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2026-09-07 18:01:25 -07:00 |
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Liangsheng Yin
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4dcecc7891
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Revert "[kernel] add fused silu mul quant fp8" (#38381)
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2026-09-07 17:36:10 -07:00 |
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Baizhou Zhang
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85d39401c8
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[CP V1 Deprecation 3.5/5] Deprecate HIP/NPU/MUSA prefill CP and remove legacy implementation (#38293)
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2026-09-07 15:39:34 -07:00 |
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Bingxu Chen
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5a5d8e47c5
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[AMD][CI] Remove obsolete split-dim check from Kimi-K3 prefill test (#38288)
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2026-09-07 14:42:53 -07:00 |
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570087ceda
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[AMD][DSV4] Reland unified-KV pool sizing and SWA ring accounting, fully gated (#38192)
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
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2026-09-07 13:13:04 -07:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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a711785475
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[Kernel] Drop the vendored dense BF16 GEMM port in favor of FlashInfer 0.6.18 (#38124)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-07 12:59:33 -07:00 |
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bf68369a18
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[ray] Support Ray metric backend for engine metrics (#31415)
Signed-off-by: Jeffrey Wang <jeffreywang@anyscale.com>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Qiaolin Yu <liin1211@outlook.com>
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2026-09-07 12:43:19 -07:00 |
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Aurick Qiao
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8392c36bce
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[Bugfix][Mamba] Clear deferred init metadata before speculative decode (#37165)
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2026-09-07 12:41:03 -07:00 |
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Shuwen Wang
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62bca081a3
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[CI] Fix request receiver EP scale joiner test patch (#38342)
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2026-09-07 23:52:32 +08:00 |
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zijiexiaandXinyuan Tong
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b5c9b68f03
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[Kimi-K3] Recover the reply when the model skips the think channel (#37743)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-07 14:08:42 +00:00 |
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62a4a6ea0e
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[NPU] Add NPU arch35 support and enhance DSV4 processing in DeepSeek-V4 (#37373)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
Co-authored-by: Kailong Lu <kelonlu@163.com>
Co-authored-by: cx <chengxin65@huawei.com>
Co-authored-by: ranjiewen <ranjiewen@huawei.com>
Co-authored-by: HEX1A0A <1a0ahex@gmail.com>
Co-authored-by: vstone-w <374330057@qq.com>
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
Co-authored-by: ClownBin <chaobin1993@126.com>
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
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2026-09-07 21:08:06 +08:00 |
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Mohammad Miadh Angkad
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c5367fa964
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[CI] Fix stale ServerArgs fake in chunked-SGMV LoRA test (#38315)
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2026-09-07 04:25:12 -07:00 |
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Shuwen Wang
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755f97c622
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[CI] Fix the DSpark dp-tier unit test fixture after #34919 (#38314)
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2026-09-07 03:16:00 -07:00 |
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Carrie ChenandBrayden Zhong
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8ae962021d
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Use fp32 in TRTLLM all reduce buffers (#36143)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
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2026-09-07 16:57:07 +08:00 |
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Cheng Wan
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b5766336d4
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[Perf] Unified memory: close the DCP decode gap on Blackwell (#37926)
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2026-09-07 01:10:44 -07:00 |
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Xiaoyu ZhangandMick Qian
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4d23a4fa6d
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[Test] Consolidate test cleanup and CI taxonomy (net -11.4K lines) (#37436)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-07 15:13:59 +08:00 |
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Ma Mingfei
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6a1ff90f2d
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[CPU] use CustomTestCase for registered CPU tests (#38244)
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2026-09-07 15:09:52 +08:00 |
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Byron HsuandByron Hsu
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a88e852fab
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[Sampling] Allow sampling-mask replay with DisallowedTokensLogitsProcessor (#38279)
Co-authored-by: Byron Hsu <24364830+ByronHsu@users.noreply.github.com>
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2026-09-06 23:56:16 -07:00 |
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