 jthomson04
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15ba54bd5d
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perf(engine): avoid timed waits for Engine responses (#39486)
Signed-off-by: jthomson04 <jwillthomson19@gmail.com>
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2026-09-21 20:42:03 -07:00 |
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Jan BernlöhrandPo-Han Huang
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56fee88e23
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fix(moe): support Llama4 NVFP4 router input weights on SM120 (#35504)
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-21 20:18:11 -07:00 |
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Kan Wu
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59a723ef1e
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[sgl-router] refactor - SLO ordering for bucket selection (#40292)
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2026-09-22 11:16:10 +08:00 |
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Kan Wu
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27f796ca6c
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[sgl-router] Fix readiness, IPv6 discovery, logging, and model validation (#40604)
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2026-09-22 11:13:06 +08:00 |
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Cheng Wan
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1d025491f3
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[Test] Set DP size in the mocked Metal profiler test (#40667)
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2026-09-21 19:57:52 -07:00 |
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90cf471723
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[AMD] [GLM-5.3-Flash Day 0] Support non-2048 top-k widths in the DSA page-table transform (#39340)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-21 19:50:17 -07:00 |
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5f9c6b9eb0
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[diffusion] fix: separate a use-scoped layerwise release from release_all (#40590)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-22 10:38:44 +08:00 |
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MickandMick Qian
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a1b2b976fe
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[diffusion] CI: restore public Qwen-Image 2.1 TP2 E2E coverage (#40507)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-22 10:38:00 +08:00 |
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Yuhan Zhou
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15eba3b464
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Feat: Add TensorCast storage as a new HiCache backend (#27265)
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2026-09-22 10:19:04 +08:00 |
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jacky.cheng
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bc30fa1759
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[AMD][Fix] AgentX HIP TPOT regression when SGLANG_SIMULATE_ACC_LEN is set (#40598)
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2026-09-21 19:16:15 -07:00 |
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Cheng Wan
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9eda772a21
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[Test] Handle tied top-k indices in graph-pool logprob regression (#40661)
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2026-09-21 19:02:43 -07:00 |
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Mohammad Miadh Angkadandmmangkad
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e332e1b84e
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[Fix] Don't write conv state from the fused KDA verify kernel (#39524)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
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2026-09-21 18:33:03 -07:00 |
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Dayananda VandClaude Opus 5
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35eb7cf8d6
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[Intel][XPU][KVCanary] Enable KV Canary on Intel XPU (#33520)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
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2026-09-22 09:19:01 +08:00 |
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Ma Mingfei
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046cd6f4ea
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[XPU][ci]: disable XPU NIXL disaggregation test (#40540)
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2026-09-22 09:02:22 +08:00 |
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Khoa Pham
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c4d3770a68
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[Kimi K3] Fix CUDA graph stream explosion (#40640)
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2026-09-21 17:49:50 -07:00 |
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jacky.cheng
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31b577bb08
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[AMD] Pad QSA MQA decode Q-heads to 16 for ROCm MFMA (#38875)
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2026-09-21 17:43:46 -07:00 |
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Cheng Wan
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98c8dee23b
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Fix lint failure from draft-decode window test location (#40654)
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2026-09-21 17:41:00 -07:00 |
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042b6a488f
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[AMD] [GLM-5.3-Flash Day 0] Enable zero-RoPE MHA prefill on ROCm (#39338)
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <45493463+kevin-mii@users.noreply.github.com>
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2026-09-21 17:38:07 -07:00 |
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Cheng Wan
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582389cec5
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[Fix] Keep diffusion encoder TP context bindings consistent (#40646)
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2026-09-21 17:23:15 -07:00 |
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Tao LiandXiaoyu Zhang
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c53cc8e1eb
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[NPU][BugFix] Avoid M-RoPE recompilation for variable sequence lengths (#40371)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-22 08:19:25 +08:00 |
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avalliappan-nvidia
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61d0cf2074
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[Spec] Windowed draft-decode attention for built-in EAGLE / MTP drafts (#32673)
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2026-09-22 08:17:57 +08:00 |
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Vedant V JhaveriandCopilot
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9fdb71732a
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Avoid materializing GDN QKV tensors during target verification (#33778)
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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2026-09-21 17:04:18 -07:00 |
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Cheng Wan
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506698761d
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[unified-memory] Hierarchical cache for every unified pool shape (#37507)
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2026-09-21 16:50:37 -07:00 |
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Cheng Wan
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22587fb15c
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[Fix] Run KV canary hooks for context-parallel prefill (#40642)
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2026-09-21 16:46:22 -07:00 |
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Yuxuan ZhangandXinyuan Tong
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00986c81be
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Support GLM-5.3-Flash hybrid attention CPU offload and PD index mapping (#40310)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-21 16:03:03 -07:00 |
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YAMY
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0229025127
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[Spec][PP] Launch extend microbatches before the spec output exchange (#40499)
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2026-09-21 15:47:03 -07:00 |
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RuibinCheung
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0c53fec476
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[ROCm] fix: remove extra bf16 -> fp32 cast in jit grouped topk kernel path (#39775)
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2026-09-21 15:43:21 -07:00 |
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Kan Wu
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d47b8c454c
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[sgl-router] Release cancelled circuit-breaker probes (#40603)
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2026-09-21 15:39:50 -07:00 |
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Liangsheng Yin
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a5c2cc517c
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[CI] Split the CI control labels into four axes and resolve them live (#40527)
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2026-09-21 15:37:28 -07:00 |
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Zhang, Jiejing
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66f19f5c46
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[AMD] Enable HiCache for GLM-5.2 MI355X throughput recipe (#40570)
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2026-09-21 15:28:27 -07:00 |
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8bde82c0ad
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[AMD] [GLM-5.3-Flash Day 0] Build the fused DSA k-pool top-k JIT kernel on HIP (#39339)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-21 15:24:44 -07:00 |
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2261c2e618
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Add MiMo-V2.6 cookbook (#40622)
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
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2026-09-21 14:58:53 -07:00 |
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Cheng Wan
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acac4dd9d9
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[Refactor] Clean up parallel runtime comments (#40632)
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2026-09-21 14:32:22 -07:00 |
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William Hu
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f532ad1f9a
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Fix GLM-5.3 forget-gate shape for nvCUTEDSL verify (#40607)
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2026-09-21 13:52:26 -07:00 |
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jacky.cheng
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e0c2e8dc4d
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[AMD] Tune Qwen3.5 TP4 GDN recurrent launch on gfx950 (#39987)
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2026-09-21 13:20:54 -07:00 |
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Liangsheng Yin
|
1ed6822039
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[Test] Anchor basic_perf thresholds to each metric's measured spread (#40617)
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2026-09-21 13:02:10 -07:00 |
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Liangsheng Yin
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b18ca9ca44
|
[CI] Bump sgl-eval to 0.1.2 (#40620)
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2026-09-21 13:00:54 -07:00 |
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11e661fd45
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[Fix] Don't free the multi-CTAs KV counter the decode graphs captured (#39175)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-21 12:58:48 -07:00 |
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Cheng Wan
|
44bdf225d8
|
Fix lint failure from MXFP8 reserved-slot test location (#40618)
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2026-09-21 12:31:11 -07:00 |
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Cheng Wan
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bccf691b22
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Bringing the parallel runtime up becomes a phase, not a side effect (#40345)
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2026-09-21 12:29:50 -07:00 |
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Cheng Wan
|
1d3243d05f
|
Take the parallel getters off the package's public surface (#40344)
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2026-09-21 12:27:50 -07:00 |
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Cheng Wan
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970e946e4f
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Retire the per-runner parallel record (#40343)
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2026-09-21 12:26:40 -07:00 |
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Cheng Wan
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73f071db52
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Deprecate the parallel getters the context answers, and ratchet them shut (#40342)
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2026-09-21 12:25:32 -07:00 |
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Cheng Wan
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65be3fa71a
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A runner and the objects it builds freeze the placement they describe (#40341)
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2026-09-21 12:24:17 -07:00 |
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Cheng Wan
|
2d0e94e3a3
|
Check the topology identities where the layout is written, and build at the published widths (#40340)
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2026-09-21 12:22:59 -07:00 |
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ishandhananiandKangyan-Zhou
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d5fdab7022
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chore: add NIXL owners and CI access (#40602)
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
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2026-09-21 12:21:30 -07:00 |
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Cheng Wan
|
0db1a93adb
|
State the draft's whole topology in its scope, and read the rest from the context (#40339)
|
2026-09-21 12:19:38 -07:00 |
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ae7a516ba7
|
feat: use XGrammar V4.1 DSML parameter constraints (#39026)
Co-authored-by: yuchuan <yuchuan.7streams@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-21 12:12:28 -07:00 |
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Faradawn Yang
|
f0940fe3a6
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Update DeepSeek-V4 Pro for B200 FP4 agentic PD disaggregation (#40610)
Signed-off-by: Faradawn Yang <73060648+faradawn@users.noreply.github.com>
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2026-09-21 12:10:03 -07:00 |
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jacky.cheng
|
90b3f8544c
|
[AMD] Use Triton softmax routing for Qwen3.5 on gfx950 (#39986)
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2026-09-21 12:02:29 -07:00 |
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