|
13dc5f2dc7
|
[HiCache][AMD] Add UMBP tiered DRAM + SSD L3 storage backend with hugepage host allocator (#25377)
Co-authored-by: TianDi101 ditian12@amd.com
Co-authored-by: Niko Ma nima@amd.com
Co-authored-by: Wu, Yutong yutong.wu@amd.com
Co-authored-by: figo fizhang@amd.com
Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
|
2026-07-01 22:21:37 +08:00 |
|
|
Mohammad Miadh Angkad
|
a0d9791810
|
[CI] Fix fused EH norm CI registration (#29845)
|
2026-07-01 21:27:07 +08:00 |
|
|
huangtingwei
|
1e80d938ff
|
[HiCache]fix draft host pool allocator type (#29823)
|
2026-07-01 19:31:16 +08:00 |
|
|
Mick
|
79f334b1aa
|
[diffusion] CI: add 5090 job (#29791)
|
2026-07-01 19:09:43 +08:00 |
|
|
Lukas Humbel
|
7d9de81cda
|
feat(hicache): Use NIXL path-mode (#27060)
|
2026-07-01 02:59:45 -07:00 |
|
|
Mohammad Miadh Angkad
|
07ca24372b
|
Add fused EH norm for DeepSeek NextN (#29667)
|
2026-07-01 02:46:21 -07:00 |
|
|
Daniel Stokes
|
8ee200972e
|
[fix] Add support for flashinfer MOE A2A to Qwen3 BF16 model path (#26255)
|
2026-07-01 01:59:54 -07:00 |
|
|
Baizhou Zhang
|
677a11bfa9
|
[Doc] Tiny update dsv4 doc (#29827)
|
2026-07-01 01:47:35 -07:00 |
|
|
ashwini rathiandSinghal, Shubham
|
5134dcdcab
|
[Intel XPU] Initially add nightly GSM8K accuracy tests for Llama-3.1-8B (TP=2) and Qwen3-32B (TP=4) (#28908)
Co-authored-by: Singhal, Shubham <shubham.singhal@intel.com>
|
2026-07-01 16:27:24 +08:00 |
|
|
Bingxu Chen
|
548f505cc5
|
[AMD] Cover DeepSeek-R1 MXFP4 TP4 MTP nightly CI (#29290)
|
2026-07-01 01:21:17 -07:00 |
|
|
Michael
|
69ce72020a
|
[AMD] Register ltx2_ada_values JIT kernel test for AMD nightly CI (#29693)
|
2026-07-01 01:13:55 -07:00 |
|
|
Bingxu Chen
|
81a472efcc
|
[AMD] Update ROCm AITER pin to 9127c94 (#29816)
|
2026-07-01 01:09:11 -07:00 |
|
|
huangtingwei
|
5e1ccd9320
|
[HiCache] Optimize HiCache hash generation with bulk token byte conversion (#28287)
|
2026-07-01 15:44:23 +08:00 |
|
|
|
df0dfbaa45
|
[Kernel] Strengthen kernel shape coverage (#29636)
Co-authored-by: Khoa Pham <khoa.pham@radixark.ai>
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
|
2026-07-01 15:44:20 +08:00 |
|
|
Xiaoyu Zhang
|
8205aa3603
|
chore: clean diffusion dead code (#29789)
|
2026-07-01 15:42:16 +08:00 |
|
|
YC Yen-Ching Tseng
|
308d89e042
|
[AMD] Split qwen3.5 triton DCP test into its own nightly job (#29409)
|
2026-07-01 00:39:39 -07:00 |
|
|
Shijin Zhang
|
00e12cebb4
|
[Fix]: Defer DSA MLA CP KV gather for fp8 trtllm prefill in PD mode (#29161)
Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
|
2026-07-01 00:20:12 -07:00 |
|
|
zhaozx-cn
|
721350656d
|
[NPU] Fix glm 4.6v (#29381)
|
2026-07-01 15:13:48 +08:00 |
|
|
Jialin Ouyang
|
40594bd381
|
[passthrough] engine: zstd request-body decompression + header overrides (#29684)
|
2026-06-30 23:48:56 -07:00 |
|
|
Xiaoyu Zhang
|
47ae1241d3
|
[CI] Relax ModelOpt NVFP4 diffusion consistency thresholds (#29767)
|
2026-07-01 14:45:08 +08:00 |
|
|
Xiaoyu Zhang
|
fcb9f229b3
|
[KDA-Pilot] Add LTX2 QKNorm split-RoPE CUDA fast path (#29708)
|
2026-07-01 14:42:07 +08:00 |
|
|
Chang Min Bark
|
41779d56fd
|
fix: make write_token dynamic (#29271)
|
2026-06-30 22:55:57 -07:00 |
|
|
Tai An
|
546d6e23ad
|
fix(mlx): default prefill_aware_swa=False on MlxModelRunnerStub (#29681)
|
2026-06-30 22:55:43 -07:00 |
|
|
Lijuan Tang
|
3cdc2415b1
|
[MLX] Fix step-bounded profiling for bench tools on Apple Silicon (#29217)
|
2026-06-30 22:55:29 -07:00 |
|
|
qinsir5522
|
a7390b17f8
|
[NPU]Modify --lora-backend & --moe-runner-backend description. (#29793)
|
2026-07-01 11:15:46 +08:00 |
|
|
|
5de66d7fbc
|
[EPD][BugFix] Fix encoder health check with global cache TP (#29296)
Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>
Co-authored-by: siyu <liusy58@linux.alibaba.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
|
2026-07-01 11:04:03 +08:00 |
|
|
zhangxiaolei
|
56f22cd520
|
Optimize C128 state pool allocation using request state pool (#28612)
|
2026-06-30 19:11:29 -07:00 |
|
|
Shijin Zhang
|
5b76f55d90
|
[Fix]: Inline H2D during CUDA graph capture to avoid stream isolation in Offloader (#29166)
Signed-off-by: Shijin Zhang <75300765+Dovis01@users.noreply.github.com>
|
2026-06-30 17:49:58 -07:00 |
|
|
weireweireandweireweire
|
a01afdd526
|
Support real draft tokens to simulated acceptance (#29645)
Co-authored-by: weireweire <20922698+weireweire@users.noreply.github.com>
|
2026-06-30 17:22:05 -07:00 |
|
|
|
53c61bd5e6
|
[bug2] skip swa recovery on locked full kv (#29352)
Co-authored-by: Zhangheng <hzh0425@apache.org>
Co-authored-by: Hanming Lu <69857889+hanming-lu@users.noreply.github.com>
|
2026-06-30 16:07:06 -07:00 |
|
|
Yuzhen Zhou
|
99b8f36cb1
|
Skip custom all-reduce v2 CUDA graph capture with torch memory saver. (#27948)
|
2026-06-30 14:53:29 -07:00 |
|
|
|
bb98629157
|
docs(cookbook): add AMD MI300X/MI325X/MI355X support for GLM-5.2 (#28471)
Co-authored-by: Claude Opus 4 (1M context) <noreply@anthropic.com>
Co-authored-by: zijiexia <37504505+zijiexia@users.noreply.github.com>
Co-authored-by: Zijie Xia <zijie.xia@radixark.ai>
|
2026-06-30 21:08:51 +00:00 |
|
|
sglang-botandsglang-bot
|
081a01c37d
|
docs: sync LMSYS SGLang blog cards (#29307)
Co-authored-by: sglang-bot <sglang-bot@users.noreply.github.com>
|
2026-06-30 20:48:10 +00:00 |
|
|
TzZtzt
|
e721259079
|
typo-fix: correct mooncake package name to "mooncake-transfer-engine" (#25153)
|
2026-06-30 11:54:36 -07:00 |
|
|
|
97fc4dfd73
|
[Doc]Checking and modifying Markdown formatting issues and link validity (#28586)
Signed-off-by: a60124901 <anyuxin4@h-partners.com>
Co-authored-by: sglang-npu-bot <sglangnpu@163.com>
Co-authored-by: ronnie_zheng <zl19940307@163.com>
|
2026-06-30 20:27:38 +03:00 |
|
|
Feng Yaoandispobock
|
1c2523b719
|
[bug1] keep full kv when swa skips leaf data (#29351)
Co-authored-by: ispobock <ispobaoke@gmail.com>
|
2026-07-01 00:51:18 +08:00 |
|
|
YC Yen-Ching Tsengandbingxche
|
c70cc96905
|
[AMD] Stop rocm720 pr auto-runs (#29768)
Co-authored-by: bingxche <bingxche@users.noreply.github.com>
|
2026-06-30 23:58:25 +08:00 |
|
|
YC Yen-Ching Tsengandbingxche
|
f2756f53f3
|
[AMD] Update AMD local registry address (#29765)
Co-authored-by: bingxche <bingxche@amd.com>
|
2026-06-30 23:40:00 +08:00 |
|
|
|
cf36dca6d4
|
[JIT Kernel] Triton moe fused gate (#25835)
Co-authored-by: Claude <noreply@anthropic.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: ziyi.xu <ziyi.xu@radixark.ai>
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-06-30 23:26:18 +08:00 |
|
|
Yihao WangandClaude Opus 4.8
|
a531d81c19
|
[diffusion][cache-dit] support Krea-2 + run-driven has_separate_cfg (#29688)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
|
2026-06-30 08:22:05 -07:00 |
|
|
Estrella-xx
|
c6a7c98ae4
|
[NPU]GLM-4.7-Flash optimize with fused kernels (#29509)
|
2026-06-30 19:22:19 +08:00 |
|
|
nvjullin
|
2f730e299f
|
Disable dsr1 prefill cudagraphs by default (#28053)
|
2026-06-30 16:34:44 +08:00 |
|
|
Stanley Winata
|
a5e6dd3767
|
[AMD] Implement QuarkW4A8MXFp4MoE to support amd/gpt-oss-120b-w-mxfp4-a-fp8 (#27204)
Signed-off-by: Stanley Winata <stanley.winata@amd.com>
|
2026-06-30 01:24:22 -07:00 |
|
|
|
89620b9169
|
[NPU] Support DeepSeek V4 Flash MTP on Ascend (#28980)
Co-authored-by: Kurkur <mccllm@qq.com>
Co-authored-by: gjsheu <gjsheu@163.com>
Co-authored-by: root <root@localhost.localdomain>
Co-authored-by: khalil2ji3mp6 <khalilzhk@gmail.com>
|
2026-06-30 16:22:13 +08:00 |
|
|
cctryandcctry
|
4b4b4af583
|
Budget EAGLE/STANDALONE draft KV pool in SWA pool configurators (#29622)
Co-authored-by: cctry <cctry@fb.com>
|
2026-06-30 00:58:33 -07:00 |
|
|
silencejade
|
ff51acd67b
|
[NPU] Qwen3-VL-8B use split_qkv_rmsnorm_rope for extend (#29627)
|
2026-06-30 15:55:50 +08:00 |
|
|
Mohammad Miadh Angkad
|
bae78a44da
|
[Deps] Bump transformers to 5.12.1 (#29393)
|
2026-06-30 00:54:01 -07:00 |
|
|
Thomas Wang
|
f920a37da4
|
[AMD] Copy decode result on forward_stream instead of copy_stream (#29642)
|
2026-06-29 23:53:48 -07:00 |
|
|
Mohammad Miadh Angkad
|
b6fceaa789
|
[DSA] Use cos_sin_cache for DSA indexer fusion (#29613)
|
2026-06-29 23:49:00 -07:00 |
|
|
|
dbb51c46ac
|
[CI] Migrate JIT tests missed by #29066 to runner_config registration (#29715)
Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Co-authored-by: Mohammad Miadh Angkad <176301910+mmangkad@users.noreply.github.com>
|
2026-06-29 23:21:14 -07:00 |
|