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113f6f080e
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[PD] Enter the custom mem pool once when allocating DCP pack buffers (#40284)
Co-authored-by: Claude Opus 5 <noreply@anthropic.com>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
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2026-09-19 19:34:58 -07:00 |
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Tri Dao
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d82d653f96
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Enable optimistic prefill for Mamba radix-cache models (#40184)
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2026-09-19 19:28:11 -07:00 |
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huangtingweiandZhangheng
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e9300f643e
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[Unified Cache][9/N] add opt-in MLA load deduplication for Mooncake Linker (#39565)
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-09-20 09:56:56 +08:00 |
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AndyLi429andAndyLi429
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d903351a66
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[NPU][bugfix] update low latency quantization input and update MXFP8 tests (#38831)
Co-authored-by: AndyLi429 <AndyLi429@noreply.gitcode.com>
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2026-09-20 09:55:30 +08:00 |
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f9c2791460
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[diffusion] model: support qwen-image-2.1 (#39983)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
Co-authored-by: BBuf <1182563586@qq.com>
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2026-09-20 09:46:09 +08:00 |
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BourneSun0527andEven Zhou
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d2f291c934
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[NPU][DSV4]dsv4 enable cpp (#39820)
Co-authored-by: Even Zhou <even.y.zhou@outlook.com>
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2026-09-20 09:17:27 +08:00 |
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YAMY
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9cc7da2ab0
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[MegaMoE] Wire Qwen MoE blocks to DeepGEMM MegaMoE (MXFP4 and NVFP4 experts) (#38080)
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2026-09-19 16:00:38 -07:00 |
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3a64faa1f2
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Fix disagg PP MTP for GLM-5.2 (#39378)
Co-authored-by: Julien Lin <jullin@nvidia.com>
Co-authored-by: YAMY1234 <74099316+YAMY1234@users.noreply.github.com>
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
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2026-09-19 13:55:07 -07:00 |
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8139a1740e
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[Scheduler] Count complete prefill bursts and their tokens (#40006)
Co-authored-by: pranjalssh <pranjalssh@fb.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
Co-authored-by: Jialin Ouyang <jialino@meta.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-19 12:56:15 -07:00 |
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Zhiqiang Xie
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7a6c652c77
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[HiCache] Auto-size the host pool to fit available host memory (#40135)
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2026-09-19 12:50:43 -07:00 |
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amd-danli103
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2305242f51
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[AMD][DSV4] fix: skip compressed-KV metadata on the draft worker in the HIP radix backend (#40205)
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2026-09-19 12:13:49 -07:00 |
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metamergebotandcctry
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9e5a62a767
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[Logprob] Serve input-logprob temporaries from CUDA-graph-pool dead space (#40038)
Co-authored-by: cctry <csycfl@gmail.com>
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2026-09-19 12:03:52 -07:00 |
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kkandwunhuang
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c5326d28a3
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[AMD] dsv4: pick kv_splits per index stream, not by occupancy alone (#39968)
Co-authored-by: wunhuang <wunhuang@amd.com>
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2026-09-19 11:53:54 -07:00 |
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7b67a96640
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[DSV4] Chunk the indexer MQA logits by query rows under a free-memory budget (#39095)
Signed-off-by: Shiki Wu <shikiw@nvidia.com>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
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2026-09-19 11:53:20 -07:00 |
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993d1fccba
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[ROCm] Widen the HiCache JIT copy rounds and enable the K-only host pool (#37152)
Co-authored-by: Xiaobo Chen <xiaobche@smci355-ccs-aus-n05-33.prov.aus.ccs.cpe.ice.amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-19 08:58:10 -07:00 |
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Xiaoyu Zhang
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76f9213a41
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[Fix] Keep mHC context out of non-V4 compiled MoE forwards (#40353)
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2026-09-19 21:41:51 +08:00 |
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Benjamin TruongandXiaoyu Zhang
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83e29d6c5a
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[perf] Optimize w4a8 MoE for glm5.2 on H200 (#38220)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
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2026-09-19 20:34:25 +08:00 |
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Xiaoyu Zhang
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7fac84b639
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[DSV4.1] Reduce mHC, metadata and small-batch router overhead (#39704)
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2026-09-19 19:51:21 +08:00 |
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DarkSharpnessandBBuf
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d1acbe0746
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[DSV4.1] Big fused wo_a quant (#39957)
Co-authored-by: BBuf <1182563586@qq.com>
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2026-09-19 19:46:53 +08:00 |
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Xiaoyu Zhang
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cb22f2451e
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[Cleanup] Deduplicate kernel tests, diffusion fixtures and benchmark helpers (#40265)
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2026-09-19 19:45:38 +08:00 |
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Xiaoyu Zhang
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0b0d2c257a
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[Fix] Repair CI fixtures and ROCm speculative tree device checks (#40325)
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2026-09-19 18:16:05 +08:00 |
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Cheng Wan
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3a5f52e144
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Record a process's placement at publish, not at group build (#40071)
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2026-09-18 23:52:37 -07:00 |
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Lianmin Zheng
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5d703de9e4
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[HiCache] Size MHA host pools from device row width (#40304)
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2026-09-18 23:37:58 -07:00 |
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Xiaoyu Zhang
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6533223502
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[Lint] Fix logits processor formatting on main (#40303)
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2026-09-19 14:31:56 +08:00 |
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Xiaozhu Mengandmxz
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111aeedd37
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[Runtime] Add decode CUDA graph hooks for eager logits processing (#40222)
Co-authored-by: mxz <mxz@fb.com>
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2026-09-18 23:27:03 -07:00 |
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6e1338dd1e
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Fix prefetch attempt cleanup on abort (#40262)
Co-authored-by: cctry <cctry@meta.com>
Co-authored-by: cctry <cctry@fb.com>
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2026-09-18 22:46:17 -07:00 |
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677c1cbdc9
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[Metrics] Propagate idle gaps across all scheduler loops (#40004)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 22:42:00 -07:00 |
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8189e3896b
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[PD] Skip singleton transfer-status all-reduces (#40003)
Co-authored-by: Pranjal Shankhdhar <pranjalssh@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
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2026-09-18 22:41:50 -07:00 |
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5b42d10edf
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fix: restrict SafeUnpickler to explicit globals (#40259)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Jihui Yang <16509088+jihuiyang@users.noreply.github.com>
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2026-09-18 22:38:11 -07:00 |
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5e9342d16f
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[PP][DeepSeek V4] Overlap communication and optimize SM120 prefill (#38792)
Co-authored-by: Yangmin Li <yangminl@nvidia.com>
Co-authored-by: YAMY <74099316+YAMY1234@users.noreply.github.com>
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2026-09-18 21:18:04 -07:00 |
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929230a6f0
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Fix GLM-OCR MTP multimodal embeddings and positions (#39088)
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-18 21:10:04 -07:00 |
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Mind Lab
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111b905bd1
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fix(openai): recover logprobs token bytes from token_id (UTF-8 fragments) (#38604)
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2026-09-18 20:30:04 -07:00 |
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DefTruthandcopilot-swe-agent[bot]
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f1fbbd17bb
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[diffusion] chore: update Cache-DiT to 1.5.1 for DMD Calibrator, SVDQuant DQ, etc (#40104)
Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
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2026-09-19 11:14:33 +08:00 |
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Vincent Liu
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090263eff6
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[VLM] avoid CUDA placement on non-CUDA platforms (#38750)
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2026-09-19 11:13:22 +08:00 |
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Alexandkpham-sgl
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c3aa09b0db
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[Kernel] Fuse hc_combine_norm for mid-size verify batches (9-96 rows) (#40208)
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
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2026-09-18 20:03:49 -07:00 |
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hmalgewattaandMick Qian
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c475ac5eaf
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[diffusion] feat: out of tree platform support (#37547)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-19 09:35:58 +08:00 |
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Xiaoyu Zhang
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986959e3c4
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[Refactor] Deduplicate kernel helpers and remove unused code (#40197)
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2026-09-19 09:27:30 +08:00 |
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Khoa PhamandCursor
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10b0bcfd18
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[PD] Allow decode radix cache and HiCache L1/L2 with DCP (#40263)
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-18 17:54:35 -07:00 |
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Cheng Wan
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fa7e83fd09
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Name the two widths of the WORLD group (#40070)
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2026-09-18 17:47:02 -07:00 |
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Cheng Wan
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81421b91e9
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One read path for every parallel name (#40069)
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2026-09-18 17:43:56 -07:00 |
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Cheng Wan
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afe71f4b9e
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Read process groups through the runtime context (#40068)
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2026-09-18 17:40:32 -07:00 |
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5931fd60ee
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Support unified memory page-envelope transfers in PD (#39477)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
Co-authored-by: Yonghao Zhuang <yhzhuang@users.noreply.github.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-09-18 17:39:50 -07:00 |
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Cheng Wan
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d0730a0e8b
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Give the attention-DP width and rank one home (#40067)
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2026-09-18 17:34:33 -07:00 |
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Lifan Shen
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8ea0ee300d
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perf(sampling): avoid GPU syncs when applying custom logit processors (#39234)
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2026-09-18 17:09:30 -07:00 |
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Alison ShaoandXinyuan Tong
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21e6c98ccb
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Fix corrupted chat prompts on mistral_common tokenizers (tool_choice auto never fires) (#39773)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-18 16:12:06 -07:00 |
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2394b231c2
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Fix Mistral3 retaining every vision-tower layer to read one (#39185)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-18 16:11:54 -07:00 |
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fa521e2758
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[MM] Copy placeholder ids to CUDA asynchronously (#40010)
Co-authored-by: metamergebot <metamergebot@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-18 16:10:37 -07:00 |
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Zhiqiang Xieandcctry
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ceb1d2e580
|
[PD] Enable optimistic prefill with buffer-only L3 write-through HiCache (#40043)
Co-authored-by: cctry <csycfl@gmail.com>
|
2026-09-18 16:04:15 -07:00 |
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5e4b94b134
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[MM] Skip VMM error gathers for text-only requests (#40005)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
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2026-09-18 16:00:43 -07:00 |
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hunhokimandHun-ho Kim
|
803f0c93d2
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Fix DSA partial DP-TP mode log to use derived attn_tp_size (#39871)
Co-authored-by: Hun-ho Kim <hunho.kim@samsung.com>
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2026-09-18 15:54:45 -07:00 |
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