 RuibinCheung
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0c53fec476
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[ROCm] fix: remove extra bf16 -> fp32 cast in jit grouped topk kernel path (#39775)
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2026-09-21 15:43:21 -07:00 |
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8bde82c0ad
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[AMD] [GLM-5.3-Flash Day 0] Build the fused DSA k-pool top-k JIT kernel on HIP (#39339)
Co-authored-by: Raiden-Makoto <Raiden-Makoto@users.noreply.github.com>
Co-authored-by: Thomas Wang <thomawan@amd.com>
Co-authored-by: Kevin Mi <mikevin920@yahoo.com>
Co-authored-by: Cursor <cursoragent@cursor.com>
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2026-09-21 15:24:44 -07:00 |
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Cheng Wan
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acac4dd9d9
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[Refactor] Clean up parallel runtime comments (#40632)
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2026-09-21 14:32:22 -07:00 |
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William Hu
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f532ad1f9a
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Fix GLM-5.3 forget-gate shape for nvCUTEDSL verify (#40607)
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2026-09-21 13:52:26 -07:00 |
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jacky.cheng
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e0c2e8dc4d
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[AMD] Tune Qwen3.5 TP4 GDN recurrent launch on gfx950 (#39987)
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2026-09-21 13:20:54 -07:00 |
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Liangsheng Yin
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b18ca9ca44
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[CI] Bump sgl-eval to 0.1.2 (#40620)
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2026-09-21 13:00:54 -07:00 |
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11e661fd45
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[Fix] Don't free the multi-CTAs KV counter the decode graphs captured (#39175)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
Co-authored-by: kpham-sgl <khoa.pham@radixark.ai>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
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2026-09-21 12:58:48 -07:00 |
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Cheng Wan
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bccf691b22
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Bringing the parallel runtime up becomes a phase, not a side effect (#40345)
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2026-09-21 12:29:50 -07:00 |
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Cheng Wan
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1d3243d05f
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Take the parallel getters off the package's public surface (#40344)
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2026-09-21 12:27:50 -07:00 |
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Cheng Wan
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970e946e4f
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Retire the per-runner parallel record (#40343)
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2026-09-21 12:26:40 -07:00 |
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Cheng Wan
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73f071db52
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Deprecate the parallel getters the context answers, and ratchet them shut (#40342)
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2026-09-21 12:25:32 -07:00 |
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Cheng Wan
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65be3fa71a
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A runner and the objects it builds freeze the placement they describe (#40341)
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2026-09-21 12:24:17 -07:00 |
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Cheng Wan
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2d0e94e3a3
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Check the topology identities where the layout is written, and build at the published widths (#40340)
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2026-09-21 12:22:59 -07:00 |
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Cheng Wan
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0db1a93adb
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State the draft's whole topology in its scope, and read the rest from the context (#40339)
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2026-09-21 12:19:38 -07:00 |
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ae7a516ba7
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feat: use XGrammar V4.1 DSML parameter constraints (#39026)
Co-authored-by: yuchuan <yuchuan.7streams@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
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2026-09-21 12:12:28 -07:00 |
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jacky.cheng
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90b3f8544c
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[AMD] Use Triton softmax routing for Qwen3.5 on gfx950 (#39986)
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2026-09-21 12:02:29 -07:00 |
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ronnie_zheng
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f702a0be29
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Revert "[Diffusion] migrate the whole _register_configs from registry.py to the model own config file" (#40611)
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2026-09-21 21:05:19 +03:00 |
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Bingxu Chen
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632919e498
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[AMD] Fix DeepSeek-R1-MXFP4 accuracy with AITER FP8 (#37762)
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2026-09-21 10:51:37 -07:00 |
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ronnie_zheng
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e6931ca889
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[Diffusion] migrate the whole _register_configs from registry.py to the model own config file (#40475)
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2026-09-21 20:45:53 +03:00 |
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cctry
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7a6191c4b9
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Preallocate HiCache MHA staging before post-capture KV sizing (#40256)
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2026-09-21 10:44:29 -07:00 |
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cctry
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7ad55e4386
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[HiCache] TMA-staged host<->device KV transfer kernel (sm_90+) (#40278)
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2026-09-21 10:38:23 -07:00 |
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William Hu
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0cb37c018c
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[KDA] Enable ReplaySSM for GLM-5.3 Flash (#40517)
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2026-09-21 10:34:08 -07:00 |
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Eric.Chin.AMDandThomas Wang
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3c71bb018a
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[AMD] Enable GLM DSA prefill top-k to the v2 kernel (#37889)
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-09-21 10:31:07 -07:00 |
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5a6a1bb883
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[mxfp8-kv] Skip writes to the reserved CUDA-graph padding slot (#35351)
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
Co-authored-by: Sam Shleifer <sam@thinkingmachines.ai>
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2026-09-22 01:21:25 +08:00 |
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Liangsheng Yin
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800613a74b
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[Test] Split the serving perf tests by topic into basic_perf/ and route their thresholds through a kit (#40505)
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2026-09-21 10:05:57 -07:00 |
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Sage
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14e9c40a72
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[Observability] Expose python/rust frontend identity in /server_info (#39993)
Signed-off-by: Sage Ahrac <sagiahrak@gmail.com>
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2026-09-21 23:32:52 +08:00 |
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hanwlax
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8faa2d6731
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[NPU][Diffusion] Disable loading latency checks in Ascend fixtures (#40544)
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2026-09-21 16:56:35 +08:00 |
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Mohammad Miadh AngkadandMohammad Angkad
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8d08dfdab7
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[Fix] Add gigachat35 to the tool-call and reasoning parser name lists (#40554)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
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2026-09-21 16:34:43 +08:00 |
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ashwini rathi
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c2f860af1c
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[ci][xpu] Record device time in the multimodal_gen perf lane (#39956)
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2026-09-21 15:39:29 +08:00 |
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b63f8416b3
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[Feature] Gigachat 3.5 support (#29189)
Co-authored-by: Stanislav Petrov <stapetrov@sberbank.ru>
Co-authored-by: Viacheslav Barinov <vvadbarinov@sberbank.ru>
Co-authored-by: Viacheslav <viacheslav.teh@gmail.com>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
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2026-09-21 14:37:55 +08:00 |
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kpjeeja
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b54d5b7c7b
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disaggregation: Fix FakeKVSender queue accumulation (#28652)
Signed-off-by: KP, Jeeja <jeeja.kp@intel.com>
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2026-09-21 14:27:05 +08:00 |
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skyler-apdx
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f5f3c38aad
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[Fix] Preserve YaRN scaling when extending rotary caches (#38786)
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2026-09-21 14:14:05 +08:00 |
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AMRUTHA MandMa Mingfei
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d20cd9d77f
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[XPU]Enable HiSparse hierarchical sparse KV cache on Intel XPU (#32792)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
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2026-09-21 14:07:49 +08:00 |
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Lianmin Zheng
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11ecdbf39f
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Clean up startup logging and streamline log audits (#40526)
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2026-09-20 22:28:35 -07:00 |
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ashwini rathi
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292e3ccc0c
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[ci][xpu] Re-seed the wan2_1_t2v_1.3b perf baseline on Arc Pro B60 (#39955)
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2026-09-21 13:04:35 +08:00 |
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jianzhao-xu
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62ba964848
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Fix: post-load staging regression breaks offload meta/sharded_gpu modes (#38779)
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2026-09-21 11:19:07 +08:00 |
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Xueshen Liu
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ab03a8e7eb
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[Perf] Fork-safe import: no CUDA context at import time, lighter argument parsing (#40201)
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2026-09-21 10:48:35 +08:00 |
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zhaozx-cn
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176dbcb85d
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[npu]add chunk gdn kernel and unify ssm state layout for ascend gdn backend (#36187)
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2026-09-21 09:51:19 +08:00 |
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WenhaoZhang
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b912db67ea
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[diffusion] fix: keep Qwen-Image 2.1 prefix KV per layer under Cache-DiT (#40472)
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2026-09-21 08:48:31 +08:00 |
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MickandMick Qian
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501b7851e4
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[diffusion] CI: guard E2E/loading latency with runner-aware baselines (#39206)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-21 08:43:22 +08:00 |
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MickandMick Qian
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3a0324fb9b
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[diffusion] optimization: reduce Qwen-Image 2.1 vae and graph warmup memory (#40481)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-09-21 08:42:02 +08:00 |
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Liangsheng Yin
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76a9065bef
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[Fix] Raise on undelivered embeddings in send_with_url, fix broken tests (#40502)
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2026-09-20 17:35:27 -07:00 |
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42875bcd2a
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fix(modelopt): dispatch NVFP4 MoE on the cached backend, not the live global (#38932)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Po-Han Huang (NVIDIA) <53919306+nvpohanh@users.noreply.github.com>
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2026-09-20 19:28:54 -04:00 |
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Mohammad Miadh Angkadandmmangkad
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2fa6b94e34
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[Perf] Fuse the glm5_next mHC attn->MLP boundary (#39200)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
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2026-09-20 16:20:37 -07:00 |
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ollybbmonster
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983e643854
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[Feature] support bf16 MoE router and mxfp4 MoE for MiMo V2 (#40448)
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2026-09-20 16:13:59 -07:00 |
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luoroger37andHank Han
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d97aed2c90
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Fix TopK v2 fallback when 16-block cluster capacity is zero (#40163)
Co-authored-by: Hank Han <hanhan7630@outlook.com>
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2026-09-21 06:41:41 +08:00 |
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f31a7bd45c
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Use pinned memory for asynchronous sampling metadata transfers (#39777)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-09-20 15:31:31 -07:00 |
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Harmya Bhatt
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95521da18d
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[DeepSeek-V4.1] Bound dense prefill indexer memory (#40217)
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2026-09-20 14:43:19 -07:00 |
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c2c3629f2d
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[Kimi-K3] O(1) expert weight lookup in load_weights (#38805)
Signed-off-by: JinYan Su <751080330@qq.com>
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
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2026-09-20 14:39:45 -07:00 |
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d229952e25
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[Fix] Preserve model runner contracts in prefill CUDA graphs (#35452)
Co-authored-by: Oasis-Git <ayw.sirius19@gmail.com>
Co-authored-by: Ke Bao <ispobaoke@gmail.com>
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2026-09-20 13:53:14 -07:00 |
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