 Zhiqiang Xie
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4e9e407d37
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[HiCache] Label radix-cache metrics per rank and split the "shrunk" prefetch reason (#39280)
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2026-09-15 17:54:04 -07:00 |
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Siyuan ChenandYuwei An
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c9a8fba991
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[DSV4][BCG] Optimize the heavy memory use of C4 Indexer when BCG is enabled (#36534)
Co-authored-by: Yuwei An <ayw.sirius19@gmail.com>
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2026-09-15 17:23:11 -07:00 |
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Liangsheng Yin
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0dabef3d30
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[misc] Fix tool-call index, graph padded-row count, and prefill-graph input_embeds refresh (#39574)
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2026-09-15 16:37:22 -07:00 |
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Lianmin Zheng
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b803cfa0c4
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Add external multimodal processors to the Rust frontend (#39329)
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2026-09-15 15:38:47 -07:00 |
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2929a39927
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Use a shared byte budget for unified hybrid-SWA memory (#36729)
Co-authored-by: yhzhuang <yhzhuang@fb.com>
Co-authored-by: Cheng Wan <cheng.wan@radixark.ai>
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2026-09-15 15:27:00 -07:00 |
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4da5599e93
|
Fix first-token metadata and reused attention-layer indexing (#39328)
Co-authored-by: Jinghui Zhang <jinghui@meta.com>
Co-authored-by: Lucia Fang <116399278+luccafong@users.noreply.github.com>
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2026-09-15 15:22:26 -07:00 |
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Liangsheng Yin
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87c9f78e99
|
[Fix][PD] Give prefill and decode their own RDMA NICs in disaggregation tests (#39584)
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2026-09-15 15:07:42 -07:00 |
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Cheng Wan
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406c9c71d8
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[Feature] Support BF16 and batch-invariant inference with DeepEP v2 (#38160)
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2026-09-15 14:30:50 -07:00 |
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YAMY
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24874f90a3
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[Test] Fix DeepGEMM batch invariance test output dtype (#39636)
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2026-09-15 12:40:28 -07:00 |
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jasonjk-parkandjasonjk
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073fdf97cc
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Generalize auxiliary outputs (#39164)
Co-authored-by: jasonjk <jasonjk@twshared0085.36.lco2.facebook.com>
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2026-09-15 12:05:13 -07:00 |
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Zhiqiang Xie
|
7f5dd19256
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[HiCache] Rework the buffer-mode storage prefetch pipeline and retry bookkeeping (#39283)
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2026-09-15 10:48:49 -07:00 |
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Shangming CaiandClaude Opus 5
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47a157f257
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[CI][Disaggregation] Fix EADDRINUSE flake in test_disaggregation_dwdp_gpt_oss (#39611)
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
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2026-09-15 23:05:05 +08:00 |
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Siyuan ChenandBJWang-ant
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832ec39cc0
|
[Intra-node PD][DSV4] Pack all layers into one batch for INTRA_NODE_NVLINK path (#38984)
Co-authored-by: BJWang-ant <wangbingjia.wbj@ant-intl.com>
|
2026-09-15 21:08:33 +08:00 |
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|
Po-Han Huang (NVIDIA)
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a2a261963f
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[CI] Fix SWA decode radix cache NIXL import (#39600)
|
2026-09-15 21:01:05 +08:00 |
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Yuxuan ZhangandXinyuan Tong
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17ba2c2e7c
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Support non-strict GLM47 tool calls with EBNF constraints (#38890)
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
|
2026-09-15 16:41:48 +08:00 |
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Liangsheng Yin
|
8565b11003
|
[misc] Trim redundant variants from the 8-gpu-h20 disaggregation test suite (#39544)
|
2026-09-15 01:24:46 -07:00 |
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Beihao ZhouandBrayden Zhong
|
37ebacb50f
|
[EPLB] Drop defensive getattr for ep_dispatch_algorithm (#31804)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
|
2026-09-15 16:14:41 +08:00 |
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Bi XueandLianmin Zheng
|
df254b0a11
|
[profiler] Label draft-runner steps DRAFT and target verify VERIFY in step spans (#38630)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
|
2026-09-15 00:57:05 -07:00 |
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|
Khoa Pham
|
e4a6b090f4
|
[CI] Run test_unified_radix_cache_kl_dcp on cutedsl_mla with bf16 KV cache (#39553)
|
2026-09-15 00:35:01 -07:00 |
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iridiumine
|
8a20062652
|
[NPU][Bugfix] Disable pinned memory to fix DeepSeek-V2 DP-attention hang (#39423)
|
2026-09-15 14:59:31 +08:00 |
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|
Liangsheng Yin
|
860fa83a9f
|
[CI] Wait for a killed test server's GPU memory before the next launch (#39545)
|
2026-09-14 23:24:37 -07:00 |
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Cui Lily
|
e687b8d6af
|
[CPU] Implement fused QK Norm and RoPE kernels (#37748)
Signed-off-by: Cui, Lily <lily.cui@intel.com>
|
2026-09-15 14:17:57 +08:00 |
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Khoa PhamandClaude Fable 5.1
|
2c37b90ad6
|
[Fix][DCP] Localize widened KV ids in MLA retraction CPU backup/restore (#39487)
Co-authored-by: Claude Fable 5.1 <noreply@anthropic.com>
|
2026-09-15 13:33:41 +08:00 |
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|
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ddd4600197
|
[Fix] HiCache startup ImportError on the pinned kernel wheel (#39516)
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
Co-authored-by: Liangsheng Yin <hnyls2002@gmail.com>
Co-authored-by: hnyls2002 <lsyincs@gmail.com>
|
2026-09-14 22:31:19 -07:00 |
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|
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6c514ab025
|
Force reasoning mode for GLM-5.3 chat templates (#39227)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
Co-authored-by: Mohammad Angkad <mohammad.angkad@radixark.ai>
Co-authored-by: Xinyuan Tong <xinyuantong.cs@gmail.com>
Co-authored-by: Xinyuan Tong <115166877+JustinTong0323@users.noreply.github.com>
|
2026-09-15 13:16:26 +08:00 |
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Yanbin Jiang
|
ebd37705e4
|
[PD][LoRA] Gate decode admission on adapter slots (#39332)
|
2026-09-15 13:11:04 +08:00 |
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|
ishandhanani
|
3f871a246c
|
feat(agent sessions): attribute stored KV cache blocks to sessions (#37482)
Signed-off-by: Ishan Dhanani <ishandhanani@gmail.com>
|
2026-09-14 21:34:49 -07:00 |
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|
Shangming Cai
|
4b186cfea5
|
[CI][PD] Skip the flaky decode HiCache file-backend disaggregation test (#39368)
|
2026-09-15 11:19:03 +08:00 |
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|
Aurick QiaoandAurick Qiao
|
5dde6e8f02
|
Fix MegaMoE buffer allocation and caching for effective SM budgets (#39223)
Co-authored-by: Aurick Qiao <6137920+aurickq@users.noreply.github.com>
|
2026-09-15 10:24:02 +08:00 |
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|
Yuan Luoandluoyuan.luo
|
99060191e7
|
[KDA] Support ReplaySSM ring-write in the fused chain-verify kernel (#36821)
Co-authored-by: luoyuan.luo <luoyuan.luo@antgroup.com>
|
2026-09-15 10:22:41 +08:00 |
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|
JoeandXiaoyu Zhang
|
a23fd557ed
|
[Kernel] Add OOT dispatch for clamp position (#38687)
Co-authored-by: Xiaoyu Zhang <1182563586@qq.com>
|
2026-09-15 10:22:21 +08:00 |
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|
raghothamandLianmin Zheng
|
c0b8725f5a
|
Fix /model_info serialization when a config value is a class (#39237)
Co-authored-by: Lianmin Zheng <lianminzheng@gmail.com>
|
2026-09-14 17:10:44 -07:00 |
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|
Yang Liuandyangliu991
|
276663a79d
|
[model-loader] Split weight loading from postprocessing (#34981)
Co-authored-by: yangliu991 <yangliu991@fb.com>
|
2026-09-14 17:10:19 -07:00 |
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|
Lianmin Zheng
|
a2b4e8888f
|
Allow CUDA VMM feature transport with the Rust frontend (#39347)
|
2026-09-14 17:09:49 -07:00 |
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|
AMD-yanfeiwang
|
0163f8ff74
|
[AMD] Fix registered HiCache host pointer aliases (#35233)
|
2026-09-14 15:49:05 -07:00 |
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|
Baizhou Zhang
|
2fca6d69aa
|
bumping sgl-deep-gemm to 0.2.0 (#39371)
|
2026-09-14 15:30:31 -07:00 |
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|
cctry
|
dad8c074e7
|
Scope prefetch cache state to the request attempt (#39318)
|
2026-09-14 15:03:03 -07:00 |
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|
paulzhang-tm
|
9128d57966
|
[Spec] Allow speculative workers to stage prefill shared reads (#38554)
|
2026-09-14 14:03:27 -07:00 |
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|
pllimax
|
7465e42b7a
|
[NPU][CI] Add CANN 9.1.0 and Ascend a5 nightly suites (#38833)
|
2026-09-14 22:39:42 +08:00 |
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|
pllimax
|
433c999dd0
|
[NPU][CI] Fix sglang.test.ascend import failure in multi-node e2e pods (#39403)
|
2026-09-14 22:23:47 +08:00 |
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|
pllimax
|
d5f1c593c1
|
[NPU] Remove temperature/top_p from Qwen3.5-397B-A17B perf test (#39047)
|
2026-09-14 21:48:50 +08:00 |
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|
Kurt Shuster
|
f81fbc749a
|
[Fix] Merge adjacent KV-row frees so a mid-page split under DCP cannot double-free (#38941)
|
2026-09-14 21:44:32 +08:00 |
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|
Liangsheng Yin
|
66c7bc838e
|
[misc] Revert #38346, #33426, #39061 and #39219 (#39405)
|
2026-09-14 03:04:07 -07:00 |
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|
amd-danli103
|
5aa9b8fb3e
|
[AMD][DSV4] feat: enable fp8 two-pool unified_kv on gfx950 (#37413)
|
2026-09-14 02:49:11 -07:00 |
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|
|
3eeb7d37f9
|
[AMD] gfx950 assembly attention: length-aware split-KV for dynamic workload (#39172)
Co-authored-by: Zijie Chen <300606707+zijiecode@users.noreply.github.com>
Co-authored-by: jacky.cheng <yichiche@amd.com>
|
2026-09-13 23:48:03 -07:00 |
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|
YC Yen-Ching Tseng
|
ce66ba2844
|
[AMD] Fix AITER FP8-Q unified-attention Test (#39360)
|
2026-09-13 23:35:24 -07:00 |
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|
Bingxu Chen
|
edf9584be9
|
[AMD][CI] Disable Wave attention test file on ROCm 10 (#39356)
|
2026-09-13 23:34:18 -07:00 |
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|
Mohammad Miadh Angkadandmmangkad
|
2fd835b9c1
|
[Fix] Don't write conv state from the fused KDA verify kernel (#39219)
Co-authored-by: mmangkad <mohammad.angkad@radixark.ai>
|
2026-09-13 21:26:57 -07:00 |
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|
Jan Bernlöhr
|
60f6f03409
|
Fix MUSA detection in compiled prefill path (#39061)
|
2026-09-13 21:23:51 -07:00 |
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|
Kurt ShusterandBaizhou Zhang
|
f2111715cd
|
[fa] Make the FlashAttention backend extensible by subclasses (#33426)
Signed-off-by: Kurt Shuster <kurt@thinkingmachines.ai>
Co-authored-by: Baizhou Zhang <sobereddiezhang@gmail.com>
|
2026-09-13 21:21:25 -07:00 |
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