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1f60ddef5d
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[PD] Introduce runtime role switching between prefill and decode (#28403)
Signed-off-by: huanglong <huanglong@linux.alibaba.com>
Signed-off-by: inkcherry <mingzhi.liu@amd.com>
Co-authored-by: huanglong <huanglong@linux.alibaba.com>
Co-authored-by: Shangming Cai <csmthu@gmail.com>
Co-authored-by: Huang Long <121648372+LLLL114@users.noreply.github.com>
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2026-09-18 01:45:12 +08:00 |
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inkcherryandDuyi-Wang
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a3bf25dc62
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[AMD] Clamp MORI intranode grid GPUs (#39763)
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
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2026-09-16 02:13:59 -07:00 |
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inkcherry
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8ad76415e2
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[PD][mori] Align prefill transfer control plane for unified control plane (#36160)
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2026-08-27 21:43:13 +08:00 |
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inkcherry
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1a91c232ea
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[AMD][CI] Add targeted Mori test labels (#36636)
Signed-off-by: inkcherry <mingzhi.liu@amd.com>
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2026-08-27 00:24:02 -07:00 |
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inkcherry
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5656de2d9a
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[PD] pool decode bootstrap HTTP sessions (#31543)
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2026-07-27 21:07:23 +08:00 |
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13dc5f2dc7
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[HiCache][AMD] Add UMBP tiered DRAM + SSD L3 storage backend with hugepage host allocator (#25377)
Co-authored-by: TianDi101 ditian12@amd.com
Co-authored-by: Niko Ma nima@amd.com
Co-authored-by: Wu, Yutong yutong.wu@amd.com
Co-authored-by: figo fizhang@amd.com
Co-authored-by: AMD-yanfeiwang <yanfei.wang@amd.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-07-01 22:21:37 +08:00 |
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inkcherryandDuyi-Wang
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eb9483b5c2
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[PD][AMD]: incremental KV transfer with decode radix cache (#26288)
Signed-off-by: inkcherry <mingzhi.liu@amd.com>
Co-authored-by: Duyi-Wang <duyi.wang@amd.com>
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2026-06-13 00:06:44 -07:00 |
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inkcherryandAlex Nails
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e5b8e3a66a
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Optimize streaming detokenizer updates (#24659)
Co-authored-by: Alex Nails <alex.nails@radixark.ai>
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2026-06-02 23:44:21 -07:00 |
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inkcherry
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3b2c730320
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[AMD] Enable dual-stream MoE on ROCm (#24005)
Signed-off-by: inkcherry <mingzhi.liu@amd.com>
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2026-05-07 02:27:24 -07:00 |
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inkcherry
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1e34cd0ba5
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PD streaming: batch notify + SSE fast path (#22658)
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2026-04-22 02:21:02 -07:00 |
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inkcherry
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4fa3482180
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[Bugfix] Add missing http_worker_ipc in session error path (#22766)
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2026-04-19 12:47:09 -07:00 |
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inkcherry
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84aaa69795
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[AMD] Use bfloat16 for correction_bias in AITER FP8 path to avoid runtime dtype conversion for dsv3 (#19843)
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2026-03-06 00:57:12 -08:00 |
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