 Zhang, Jiejing
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66f19f5c46
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[AMD] Enable HiCache for GLM-5.2 MI355X throughput recipe (#40570)
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2026-09-21 15:28:27 -07:00 |
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993d1fccba
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[ROCm] Widen the HiCache JIT copy rounds and enable the K-only host pool (#37152)
Co-authored-by: Xiaobo Chen <xiaobche@smci355-ccs-aus-n05-33.prov.aus.ccs.cpe.ice.amd.com>
Co-authored-by: HAI <hixiao@gmail.com>
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2026-09-19 08:58:10 -07:00 |
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Zhang, Jiejing
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6331e43081
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[AMD] Prefer HIP Top-K for GLM-5.x on ROCm (#39631)
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2026-09-15 20:55:57 -07:00 |
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Zhang, Jiejingandfanxingran
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f920be4b09
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[AMD] GLM-5.2 NextN: cast draft fused MoE to per-channel FP8 (#39155)
Co-authored-by: fanxingran <xingran.fan@amd.com>
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2026-09-15 18:56:48 -07:00 |
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Zhang, Jiejing
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288627e400
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[AMD] Document GLM-5.2 MXFP4 recipe update on MI355X (#39230)
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2026-09-12 15:57:15 -07:00 |
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Zhang, Jiejing
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d7c284b894
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[AMD] Use the triton DSA backend for GLM-5.2 MXFP4 on MI355X (#39106)
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2026-09-11 11:48:50 -07:00 |
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Zhang, Jiejing
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6cee9285a3
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[ROCm] Make DSA indexer top-k exact with cooperative selection (#37591)
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2026-09-05 23:55:56 -07:00 |
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