6 Commits
Author SHA1 Message Date
72078cd7f5 [XPU] Support GPT-OSS MXFP4 checkpoints on Intel XPU (#35751)
Co-authored-by: Meng, Hengyu <hengyu.meng@intel.com>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-04 14:20:28 +08:00
Juan MunetonandMa Mingfei cac3269305 [XPU] Fix NemotronH (hybrid mamba2) launch on --device xpu (#32227)
Co-authored-by: Ma Mingfei <mingfei.ma@intel.com>
2026-08-12 13:23:23 +08:00
ea66b2cca7 [XPU] Enable NVIDIA-Nemotron-3-Nano-30B-A3B-BF16 on Intel XPU backend (#24390)
Co-authored-by: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: Yao Matrix <matrix.yao@intel.com>
2026-06-09 09:46:12 +08:00
2c8357f794 [XPU] Enable Gemma 4 E2B / E4B / 31B/ 26B-A4B on Intel XPU (#23280)
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Co-authored-by: jmunetong <jmunetong@users.noreply.github.com>
Co-authored-by: Meng, Hengyu <hengyu.meng@intel.com>
Co-authored-by: ckvermaAI <ckverma@habana.ai>
2026-06-05 10:05:07 +08:00
Juan MunetonandKangyan-Zhou 4052b53227 fix scheduler for non-cuda devices and disable piecewise cuda graph f… (#19992)
Co-authored-by: Kangyan-Zhou <zky314343421@gmail.com>
2026-03-18 21:54:19 -07:00
Juan MunetonandYang Wang 7458407437 Fix InternVL and vision attention for non-CUDA backends (e.g. XPU) (#19997)
Co-authored-by: Yang Wang <mr.yang.wang@outlook.com>
2026-03-14 23:24:41 -07:00