docs(cookbook): update Kimi-K3 GB200 recipes from measured 4x4 runs (#32592)
Co-authored-by: Lee Nau <lnau@nvidia.com>
This commit is contained in:
@@ -1274,9 +1274,82 @@ export const config = {
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],
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},
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{
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// PP16 x TP1 spans all 16 ranks. Prefill tok/s/GPU at ISL 8192,
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// concurrency 32: 4550 here vs 3596 (PP8 x TP2), 2407 (TEP16), 1652 (TP16);
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// flat past 32. Below concurrency ~8 the pipeline cannot fill and TEP16
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// leads instead (1947 vs 1227) — use `--tp-size 16 --ep-size 16` there.
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// That four-way comparison was measured aggregated at OSL 1; the shape
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// itself is as-run in this PD role. Pairs with the Balanced and
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// High-Throughput decode cells; the Low-Latency decode cell runs pp=2 and
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// needs a PP2 x TP8 prefill instead.
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match: { hw: "gb200", pdMode: "prefill", strategy: "default" },
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nnodes: 4,
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verified: false,
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verificationStatus: "in-progress",
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env: [
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"SGLANG_ENABLE_TP_MEMORY_INBALANCE_CHECK=0",
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],
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flags: [
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"--trust-remote-code",
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"--model-path {{MODEL_NAME}}",
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"--tp-size 1",
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"--pp-size 16",
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"--mem-fraction-static 0.85",
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"--chunked-prefill-size 16384",
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"--max-prefill-tokens 16384",
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"--disable-flashinfer-autotune",
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"--weight-loader-prefetch-checkpoints",
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"--reasoning-parser kimi_k3",
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"--tool-call-parser kimi_k3",
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"--disaggregation-mode prefill",
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"--disaggregation-transfer-backend nixl",
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"--disaggregation-bootstrap-port 8998",
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"--host {{HOST_IP}}",
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"--port {{PORT}}",
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],
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},
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{
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// Same chunked-PP shape as the Default cell, with mem-fraction raised to
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// 0.90 for KV headroom — the B300/GB300 Long-Context recipes make the same
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// trade. Keeping TP at 1 is what buys the context length here: with TP > 1
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// the MLA KV is replicated across the TP ranks, so TP2 x PP8 would hold
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// roughly half the tokens of TP1 x PP16 for the same memory.
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// Not yet benchmarked on long-context workloads.
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match: { hw: "gb200", pdMode: "prefill", strategy: "long-context" },
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nnodes: 4,
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verified: false,
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verificationStatus: "in-progress",
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env: [
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"SGLANG_ENABLE_TP_MEMORY_INBALANCE_CHECK=0",
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],
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flags: [
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"--trust-remote-code",
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"--model-path {{MODEL_NAME}}",
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"--tp-size 1",
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"--pp-size 16",
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"--mem-fraction-static 0.90",
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"--chunked-prefill-size 16384",
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"--max-prefill-tokens 16384",
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"--disable-flashinfer-autotune",
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"--weight-loader-prefetch-checkpoints",
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"--reasoning-parser kimi_k3",
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"--tool-call-parser kimi_k3",
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"--disaggregation-mode prefill",
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"--disaggregation-transfer-backend nixl",
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"--disaggregation-bootstrap-port 8998",
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"--host {{HOST_IP}}",
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"--port {{PORT}}",
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],
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},
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// ----- Decode role: the unified cell for the same hw and strategy, plus
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// the PD role and transport flags, and re-sized KDA state.
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//
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// GB200 decode figures below: ISL 8192 / OSL 1024, 16 GPU decode, behind a
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// shared PP2 x TP8 prefill. Comparisons hold; absolutes would be higher
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// behind the PP16 x TP1 prefill cell above.
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//
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// Decode runs the KV cache as a chunk cache, so the unified 5-slots-per-
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// request reservation (1 state + ping-pong copies for radix reuse) drops to
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// a single slot, and --mamba-radix-cache-strategy stops having any effect.
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@@ -1722,18 +1795,25 @@ export const config = {
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],
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},
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{
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// PP2 x TP8 is the fastest decode shape below concurrency ~100:
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// 13.3 out tok/s/GPU @ 57.7 out tok/s/user at concurrency 8, against
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// 9.5 @ 40.7 (TP16), 9.3 @ 39.9 (DCP16) and 9.3 @ 39.7 (DCP16+EP16) —
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// +40% throughput and +45% interactivity over the best pp=1 shape. It
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// stays ahead through concurrency 64 and is overtaken by DCP16+EP16 at 128.
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// Measured without --enable-symm-mem.
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match: { hw: "gb200", pdMode: "decode", strategy: "low-latency" },
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nnodes: 4,
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verified: false,
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verificationStatus: "in-progress",
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warn: "SGLang requires `decode pp_size == prefill pp_size or 1`, so this cell must be paired with a PP2 x TP8 prefill (`--tp-size 8 --pp-size 2`) rather than the PP16 x TP1 Prefill recipe. That prefill delivers 2919 prefill tok/s/GPU against PP16's 4550, which is the trade for the decode-side latency.",
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env: [
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"SGLANG_ENABLE_TP_MEMORY_INBALANCE_CHECK=0",
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],
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flags: [
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"--trust-remote-code",
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"--model-path {{MODEL_NAME}}",
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"--tp-size 16",
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"--enable-symm-mem",
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"--tp-size 8",
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"--pp-size 2",
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"--mem-fraction-static 0.85",
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"--disaggregation-decode-extra-slots 16",
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"--reasoning-parser kimi_k3",
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@@ -1745,6 +1825,9 @@ export const config = {
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],
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},
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{
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// EP16 on top of DCP16 is +6% to +10% out tok/s/GPU at every concurrency
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// measured, at the same batch size: 56.2 vs 52.4 (c64), 92.7 vs 84.5
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// (c128), 136.1 vs 126.1 (c256), 153.5 vs 144.2 (c512).
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match: { hw: "gb200", pdMode: "decode", strategy: "balanced" },
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nnodes: 4,
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verified: false,
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@@ -1757,6 +1840,7 @@ export const config = {
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"--model-path {{MODEL_NAME}}",
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"--tp-size 16",
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"--dcp-size 16",
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"--ep-size 16",
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"--mem-fraction-static 0.85",
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"--disaggregation-decode-extra-slots 16",
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"--reasoning-parser kimi_k3",
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@@ -1768,6 +1852,16 @@ export const config = {
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],
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},
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{
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// Grouping DCP as 8 x dp2 rather than a flat DCP16 is what makes MegaMoE
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// pay off here. out tok/s/GPU @ out tok/s/user, concurrency 256 / 512:
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// DCP8 x dp2 + EP16 145.5 @ 25.4 157.5 @ 25.2 <- this cell
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// DCP16 + EP16 136.1 @ 20.6 153.5 @ 17.5
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// DCP16 126.1 @ 18.7 144.2 @ 16.1
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// TP16 87.4 @ 23.9 90.2 @ 23.9 (batch caps at ~125)
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// Pair this cell with MegaMoE in the MoE Parallelism card: +8.3% / +10.0% /
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// +11.0% over FlashInfer MXFP4 at concurrency 64 / 128 / 256, and the
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// combination validated to concurrency 512. The gain needs dp > 1 — on the
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// flat DCP16 cell MegaMoE is the slower of the two below concurrency 256.
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match: { hw: "gb200", pdMode: "decode", strategy: "high-throughput" },
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nnodes: 4,
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verified: false,
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@@ -1779,8 +1873,11 @@ export const config = {
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"--trust-remote-code",
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"--model-path {{MODEL_NAME}}",
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"--tp-size 16",
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"--dcp-size 16",
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"--mem-fraction-static 0.92",
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"--dcp-size 8",
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"--dp-size 2",
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"--enable-dp-attention",
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"--ep-size 16",
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"--mem-fraction-static 0.85",
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"--disaggregation-decode-extra-slots 16",
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"--reasoning-parser kimi_k3",
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"--tool-call-parser kimi_k3",
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@@ -1802,6 +1899,15 @@ export const config = {
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" SGLANG_HOST_IP=<this-node-ip>",
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" NCCL_IB_HCA=<hca0,hca1,...> # RDMA fabrics only",
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],
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gb200: [
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"Allocate all four nodes within a single NVL72 domain.",
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"MNNVL is off by default — set on every rank:",
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" NCCL_MNNVL_ENABLE=1",
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" NCCL_CUMEM_ENABLE=1",
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"Point the JIT caches at GB200-only paths; GB200 is SM100 and GB300 is SM103,",
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"so the two architectures need separate caches:",
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" TORCH_EXTENSIONS_DIR / TRITON_CACHE_DIR / TVM_FFI_CACHE_DIR",
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],
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h100: [
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"Set This node IP separately on each node; use the same cross-node NIC name on all four nodes.",
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],
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