docs: add NVFP4 quantization option to Kimi-K3 deploy panel (#35168)
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@@ -40,7 +40,7 @@ For how to launch the image, see [Install → Method 3: Using Docker](../../../d
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</Accordion>
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Pick your hardware, then the deployment shape and operating point. Node count follows the hardware recipe (B200 2×8, GB200 4×4, H100 4×8, B300 1×8, H200 2×8 — 4×8 on Unified High-Throughput, GB300 2×4, MI350X/MI355X 1×8), so it is not a separate choice.
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Pick your hardware, then the deployment shape and operating point. Node count follows the hardware recipe (B200 2×8, GB200 4×4, H100 4×8, B300 1×8, H200 2×8 — 4×8 on Unified High-Throughput, GB300 2×4, MI350X/MI355X 1×8), so it is not a separate choice. If you serve the NVFP4 checkpoint (`nvidia/Kimi-K3-NVFP4`, the **Quantization** row in the panel below), use the `lmsysorg/sglang:dev-dev-kimi-k3-nvfp4` image.
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**PD Mode** — `Unified` serves prefill and decode together. `Prefill` / `Decode` split them into dedicated pools (see [PD disaggregation](#3-4-pd-disaggregation)); `Prefill` ships two strategies, both chunked at 16k. On the 8-GPU platforms (B300 1×8, GB300 2×4), `Default` is TP8 and `Long-Context` is `--pp-size 8 --tp-size 1`. On the 16-GPU platforms (B200 2×8, GB200 4×4), both are `--pp-size 16 --tp-size 1` and differ only in `--mem-fraction-static` (0.85 vs 0.90) — deep PP is the throughput shape there, not just the long-context one (see [Deep PP](#deep-pp-for-prefill)).
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@@ -160,6 +160,39 @@ export const config = {
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// Orthogonal to the cell grid: the picked option layers flags onto whichever
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// cell is showing, so turning speculation on does not triple the cell count.
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overlayDims: [
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{
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// Checkpoint choice, orthogonal to the cell grid: MXFP4 is the shipping
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// default, NVFP4 is NVIDIA's ModelOpt mixed checkpoint (NVFP4 SiTU routed
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// experts + FP8_PB_WO 128x128 block-FP8 attention). NVFP4 swaps the model
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// slug (modelNames) and pins the TRT-LLM MoE runner — the auto resolution
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// never engages TRT-LLM deferred finalize and the NVFP4 MoE raises
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// NotImplementedError at CUDA-graph capture, while flashinfer_cutlass has
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// no SiTU kernel. The DSPARK overlay needs no change: the same draft
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// checkpoint serves on top of the NVFP4 base.
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id: "quant",
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title: "Quantization",
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default: "mxfp4",
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options: [
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{ id: "mxfp4", label: "MXFP4", subtitle: "Moonshot AI checkpoint" },
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{
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id: "nvfp4",
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label: "NVFP4",
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subtitle: "NVIDIA checkpoint",
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// The NVFP4 MoE kernels (FlashInfer TRT-LLM) are Blackwell-only.
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disabled: (s) => !["b200", "gb200", "b300", "gb300"].includes(s.hw),
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disableReason:
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"The nvidia/Kimi-K3-NVFP4 checkpoint needs Blackwell: its routed experts run on FlashInfer TRT-LLM NVFP4 kernels (SiTU), which do not exist for Hopper or AMD.",
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// B200's Balanced/High-Throughput cells pin flashinfer_mxfp4; Hopper
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// pins marlin (unreachable here — NVFP4 is Blackwell-gated). Replace
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// whatever the cell pins with the one working NVFP4 runner.
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stripPrefixes: ["--moe-runner-backend"],
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flags: ["--moe-runner-backend flashinfer_trtllm"],
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hints: [
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"Use docker image lmsysorg/sglang:dev-dev-kimi-k3-nvfp4 (CUDA 13).",
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],
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},
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],
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},
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{
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id: "mmTransport",
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title: "VLM Transport",
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@@ -333,6 +366,7 @@ export const config = {
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modelNames: {
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default: "moonshotai/Kimi-K3",
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nvfp4: "nvidia/Kimi-K3-NVFP4",
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},
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placeholders: {
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@@ -379,6 +413,12 @@ export const config = {
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gb200: "lmsysorg/sglang:kimi-k3",
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mi350x: "lmsysorg/sglang-rocm:rocm720-mi35x-k3-20260727",
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mi355x: "lmsysorg/sglang-rocm:rocm720-mi35x-k3-20260727",
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// NVFP4 needs a build with sgl-project/sglang#35077; the purpose-built dev
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// image is cut from that PR's head (CUDA 13).
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"b300|nvfp4": "lmsysorg/sglang:dev-dev-kimi-k3-nvfp4",
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"gb300|nvfp4": "lmsysorg/sglang:dev-dev-kimi-k3-nvfp4",
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"b200|nvfp4": "lmsysorg/sglang:dev-dev-kimi-k3-nvfp4",
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"gb200|nvfp4": "lmsysorg/sglang:dev-dev-kimi-k3-nvfp4",
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},
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// Pre-selects the issue template's `model` field on "Submit verified cell".
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github: {
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