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[AMD][CI] Limit HiCache MGSM eval concurrency on ROCm (#36308)

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Bingxu Chen
2026-08-28 01:05:59 -07:00
committed by GitHub
parent 2960d69622
commit 2a7fb511c9
1 changed files with 2 additions and 0 deletions
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test/registered/hicache/test_hicache_variants.py
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@@ -81,6 +81,8 @@ class TestHiCacheMLA(HiCacheBaseServer, MMLUMixin, MGSMEnMixin):
mmlu_num_examples = 256 mmlu_num_examples = 256
mmlu_num_threads = 32 mmlu_num_threads = 32
mgsm_en_score_threshold = 0.8 mgsm_en_score_threshold = 0.8
if _is_hip:
mgsm_en_num_threads = 32
@unittest.skipIf(is_hip(), "Disabled for AMD-aiter") @unittest.skipIf(is_hip(), "Disabled for AMD-aiter")