From 2a7fb511c94840aac7766d37788c72b963a90d0c Mon Sep 17 00:00:00 2001 From: Bingxu Chen Date: Fri, 28 Aug 2026 16:05:59 +0800 Subject: [PATCH] [AMD][CI] Limit HiCache MGSM eval concurrency on ROCm (#36308) --- test/registered/hicache/test_hicache_variants.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/registered/hicache/test_hicache_variants.py b/test/registered/hicache/test_hicache_variants.py index 419ef37f0..1f130dd2d 100644 --- a/test/registered/hicache/test_hicache_variants.py +++ b/test/registered/hicache/test_hicache_variants.py @@ -81,6 +81,8 @@ class TestHiCacheMLA(HiCacheBaseServer, MMLUMixin, MGSMEnMixin): mmlu_num_examples = 256 mmlu_num_threads = 32 mgsm_en_score_threshold = 0.8 + if _is_hip: + mgsm_en_num_threads = 32 @unittest.skipIf(is_hip(), "Disabled for AMD-aiter")