Aditya SharmaandXiaodong Ye b2eed9e16d [Apple Silicon] Add custom Metal RoPE kernel with fused KV cache store (#22868) ...

Signed-off-by: Xiaodong Ye <yeahdongcn@gmail.com>
Co-authored-by: Xiaodong Ye <yeahdongcn@gmail.com>

2026-05-29 15:09:33 +08:00

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advanced_features

Support Flashinfer Cute-DSL MLA attention (#24737)

2026-05-28 00:21:32 -07:00

basic_usage

[Refactor] Rename NSA → DSA: user-facing aliases, file/class/import rename (#25821)

2026-05-20 00:18:04 -07:00

developer_guide

bench_serving: add Zipfian shared-prefix sampling to generated-shared-prefix (#26378)

2026-05-28 14:39:46 -07:00

get-started

[Doc] Update pip install commands for Cuda12 (#26344)

2026-05-25 22:28:27 -07:00

hardware-platforms

[Apple Silicon] Add custom Metal RoPE kernel with fused KV cache store (#22868)

2026-05-29 15:09:33 +08:00

references

[Bugfix] [DSA] [Hisparse] Broadcast TP Rank 0 Topk Indexes to other TPs (#24654)

2026-05-28 21:14:46 -07:00

sglang-diffusion

[Diffusion] Default NVFP4 backend to FlashInfer TRTLLM (#25523)

2026-05-25 18:14:06 +08:00

supported-models

[Model] Laguna-XS.2 Model Support (#24204)

2026-05-09 05:43:13 +08:00

supported-models.mdx

[Docs] Sync docs_new with legacy docs and update migration redirects (#23337)

2026-04-21 00:15:17 -07:00