Aditya SharmaandXiaodong Ye b2eed9e16d [Apple Silicon] Add custom Metal RoPE kernel with fused KV cache store (#22868) ...

Signed-off-by: Xiaodong Ye <yeahdongcn@gmail.com>
Co-authored-by: Xiaodong Ye <yeahdongcn@gmail.com>

2026-05-29 15:09:33 +08:00

..

sglang

[Apple Silicon] Add custom Metal RoPE kernel with fused KV cache store (#22868)

2026-05-29 15:09:33 +08:00

tools

Fix get_version_tag.py to handle dot-separated post versions (#22385)

2026-04-08 15:18:22 -07:00

pyproject_cpu.toml

Upgrade xgrammar to 0.2.1 (#25676)

2026-05-29 11:40:07 +08:00

pyproject_npu.toml

Upgrade xgrammar to 0.2.1 (#25676)

2026-05-29 11:40:07 +08:00

pyproject_other.toml

Upgrade xgrammar to 0.2.1 (#25676)

2026-05-29 11:40:07 +08:00

pyproject_xpu.toml

Upgrade xgrammar to 0.2.1 (#25676)

2026-05-29 11:40:07 +08:00

pyproject.toml

Upgrade xgrammar to 0.2.1 (#25676)

2026-05-29 11:40:07 +08:00