Zhanghengand晟海 6a9366f036 [Unified Cache Linker][2/N]: Add device pool assembly for external linkers (#37098) ...

Co-authored-by: 晟海 <huangtingwei.htw@antgroup.com>

2026-08-30 23:54:00 +08:00

..

sglang

[Unified Cache Linker][2/N]: Add device pool assembly for external linkers (#37098)

2026-08-30 23:54:00 +08:00

MANIFEST.in

[Kernel] Move sgl-kernel under sglang.kernels.aot (#32648)

2026-07-29 17:25:00 +08:00

pyproject_cpu.toml

[Chore] Move version tag helper to release scripts (#35196)

2026-08-18 00:11:12 -07:00

pyproject_npu.toml

[Chore] Move version tag helper to release scripts (#35196)

2026-08-18 00:11:12 -07:00

pyproject_other.toml

[MLX] Upgrade to Torch 2.13/MLX 0.32+ and redesign the Torch-MLX tensor bridge (#32984)

2026-08-21 18:51:42 -07:00

pyproject_xpu.toml

[Chore] Move version tag helper to release scripts (#35196)

2026-08-18 00:11:12 -07:00

pyproject.toml

Bump sgl-deep-gemm to v0.1.6 (#36998)

2026-08-29 19:51:02 -07:00

setup.py

Build Rust extensions on demand in source checkouts (#34994)

2026-08-16 14:58:06 -07:00