Bob ChenandZhiqiang Xie 7cd55c6818 [HiCache] Optimize L2 mem allocation when cache miss in L3 (#19320) ...

Co-authored-by: Zhiqiang Xie <xiezhq@stanford.edu>

2026-07-16 15:00:53 -07:00

..

sglang

[HiCache] Optimize L2 mem allocation when cache miss in L3 (#19320)

2026-07-16 15:00:53 -07:00

tools

Fix get_version_tag.py to handle dot-separated post versions (#22385)

2026-04-08 15:18:22 -07:00

pyproject_cpu.toml

Add Accuracy Benchmark for OCR models (#25364)

2026-07-06 16:18:43 +08:00

pyproject_npu.toml

Add Accuracy Benchmark for OCR models (#25364)

2026-07-06 16:18:43 +08:00

pyproject_other.toml

Add Accuracy Benchmark for OCR models (#25364)

2026-07-06 16:18:43 +08:00

pyproject_xpu.toml

Add Accuracy Benchmark for OCR models (#25364)

2026-07-06 16:18:43 +08:00

pyproject.toml

chore: bump tokenspeed_mla to 0.1.8 (#31385)

2026-07-15 22:37:54 -07:00

setup.py

Gate Rust extension builds (#30927)

2026-07-12 05:44:58 -07:00