Cheng Wan 2d0e94e3a3 Check the topology identities where the layout is written, and build at the published widths (#40340)

2026-09-21 12:22:59 -07:00

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diffusion

[diffusion] fix: recover ipc jit initialization after interrupted builds (#39034)

2026-09-11 19:34:09 +08:00

disaggregation

[PD][LoRA] Gate decode admission on adapter slots (#39332)

2026-09-15 13:11:04 +08:00

dp_attn

Re-land dp-attention local control broadcast test (#39835)

2026-09-17 14:33:25 +08:00

dsv4

[AMD][DSV4] feat: enable DSpark with fp8 unified_kv on gfx950 (#38901)

2026-09-20 01:16:39 -07:00

gdn

Fix Qwen3.5 GDN multi-item scoring (#33922)

2026-09-09 22:30:39 -07:00

hicache

[HiCache][LoRA] Isolate storage pages by extra key (#38577)

2026-09-12 18:18:14 +08:00

layers

[Logprob] Serve input-logprob temporaries from CUDA-graph-pool dead space (#40038)

2026-09-19 12:03:52 -07:00

lora

[LoRA] Support MoE in full and breakable prefill CUDA graphs (#38578)

2026-09-11 14:40:02 -07:00

models

[CI] Give the kernel lane a 5090 suite and move kernel-only tests off the general lane (#40496)

2026-09-20 16:46:53 -07:00

models_large

[Test] Drop dead and strictly-subsumed CI test registrations (#40264)

2026-09-18 17:49:13 -07:00

pp

Check the topology identities where the layout is written, and build at the published widths (#40340)

2026-09-21 12:22:59 -07:00

speculative

feat: support TP>1 Domino rollout for DFlash V2 (#37069)

2026-09-11 18:51:11 -07:00

xpu

[XPU] Use torch scaled_mm for XPU block FP8 linear (#35605)

2026-09-16 10:10:31 +08:00